July 2005

ASM5I9352

rev 0.2

2.5V or 3.3V, 200 MHz, 11-Output Zero Delay Buffer

3 of 12

Notice: The information in this document is subject to change without notice.

Pin Configuration

1

Pin

Name

I/O

Type

Description

6

REFCLK

I, PD

LVCMOS

Reference clock input

.

12, 14,

15, 18, 19

QA(0:4)

O

LVCMOS

Clock output bank A

.

22, 23,

26, 27

QB(0:3)

O

LVCMOS

Clock output bank B

.

30, 31

QC(0,1)

O

LVCMOS

Clock output bank C

.

8

FB_IN

I, PD

LVCMOS

Feedback clock input

. Connect to an output for normal operation.

This input should be at the same voltage rail as input reference

clock. See Table 1.

1

VCO_SEL

I, PD

LVCMOS

VCO divider select input

. See Table 2.

5

MR/OE#

I, PD

LVCMOS

Master reset/output enable/disable input

. See Table 2.

9

PLL_EN#

I, PD

LVCMOS

PLL enable/disable input

. See Table 2.

2, 3, 4

SEL(A:C)

I, PD

LVCMOS

Frequency select input, Bank (A:C)

. See Table 2.

16, 20

Supply

2.5V or 3.3V power supply for bank A output clocks

21, 25

Supply

2.5V or 3.3V power supply for bank B output clocks

.

2,3

32

Supply

2.5V or 3.3V power supply for bank C output clocks

.

2,3

10

Supply

2.5V or 3.3V power supply for PLL

.

2,3

11

Supply

2.5V or 3.3V power supply for core and inputs

.

2,3

7

Supply

Ground

Analog ground

.

13, 17,

24, 28, 29

Supply

Ground

Common ground

.

Note: 1. PD = Internal pull-down.

2.A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins

their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.

3.AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output

supply pins.