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MCP47CMB21 Datasheet(PDF) 3 Page - Microchip Technology |
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MCP47CMB21 Datasheet(HTML) 3 Page - Microchip Technology |
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3 / 124 page  2018-2019 Microchip Technology Inc. DS20006089B-page 3 MCP47CXBXX MCP47CMBX2 Block Diagram (Dual Channel Output) VDD VSS Memory VREF0(2) SDA SCL VREF1:VREF0 Note 1: On dual output devices, except those in a QFN16 package, the LAT0 pin is internally connected to LAT1 input of DAC1. 2: On dual output devices, except those in a QFN16 package, the VREF0 pin is internally connected to VREF1 input of DAC1. A0 A1 VOUT0 VDD LAT0/HVC PD1:PD0 VREF1:VREF0 OP AMP ADDR6:ADDR0 PD1:PD0 and VREF1:VREF0 DAC0 and DAC1 VREF POWER-DOWN GAIN STATUS DAC0 and DAC1 VREF POWER-DOWN GAIN/I2C ADDRESS WiperLock™ VOLATILE (5x16) NONVOLATILE (14x16) Band Gap 1.214V VDD GAIN VREF1(2) VREF1:VREF0 VOUT1 VDD LAT1(1) PD1:PD0 VREF1:VREF0 OP AMP PD1:PD0 and VREF1:VREF0 VDD GAIN VIHH LAT0 LAT0(1) VBG VBG Power-up/Brown-out Control I2C Serial Interface Module and Control Logic (WiperLock™ Technology) |
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