MCP47CMB21 datasheet(49/124 Pages) MICROCHIP

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DS20006089B-page 49

MCP47CXBXX

4.1.2

BROWN-OUT RESET

A Brown-out Reset occurs when a device had power

applied to it and that power (voltage) drops below the

specified range.

When the falling VDD voltage crosses the VPOR trip

point (BOR event), the following occurs:

• Serial interface is disabled.

• MTP writes are disabled.

• Device is forced into a power-down state

(PDxB:PDxA = 11). Analog circuitry is turned off.

• Volatile DAC register is forced to 000h.

Volatile Configuration bits, VRxB:VRxA and Gx, are

forced to ‘0’.

If the VDD voltage decreases below the VRAM voltage,

all volatile memory may become corrupted.

As the voltage recovers above the VPOR/VBOR voltage,

see Section 4.1.1 “Power-on Reset” for further details.

Serial commands not completed due to a brown-out

condition may cause the memory location to become

corrupted.

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

4.2

Device Memory

User memory includes the following types:

• Volatile Register Memory (RAM)

• Nonvolatile Register Memory (MTP)

MTP memory is present just for the MCP47CMBXX

devices and has three groupings:

• NV DAC Output Values (loaded on POR event)

• Device Configuration Memory

• General Purpose NV Memory

Each memory location is up to 16 bits wide. The

memory-mapped register space is shown in Table 4-1.

The I2C interface depends on how this memory is read

and written. Refer to Section 6.0 “I2C Serial Interface

Module” and Section 7.0 “Device Commands” for

more details on reading and writing the device’s

memory.

4.2.1

VOLATILE REGISTER MEMORY

(RAM)

The MCP47CXBXX devices have volatile memory to

directly control the operation of the DACs. There are

up to five volatile memory locations:

• DAC0 and DAC1 Output Value registers

• VREF Select register

• Power-Down Configuration register

• Gain and Status register

The volatile memory starts functioning when the

device VDD is at (or above) the RAM retention voltage

(VRAM). The volatile memory will be loaded with the

default device values when the VDD rises across the

VPOR/VBOR voltage trip point.

After the device is powered-up, the user can update the

device memory. Table 4-2 shows the volatile memory

locations and their interaction due to a POR event.

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