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MCP47CMB21 Datasheet(PDF) 75 Page - Microchip Technology

Part # MCP47CMB21
Description  8/10/12-Bit Digital-to-Analog Converters, 1 LSb INL Single/Dual Voltage Outputs with I2C Interface
PDF  124 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP47CMB21 Datasheet(HTML) 75 Page - Microchip Technology

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 2018-2019 Microchip Technology Inc.
DS20006089B-page 75
MCP47CXBXX
7.5.3
SINGLE WRITE TO NONVOLATILE
MEMORY (HVC PIN = VIHH)
The sequence to write to a single nonvolatile memory
location is the same as a single write to volatile memory,
with the exception that the MTP Write Cycle (twc) is
started after a properly formatted command, including
the Stop bit, is received. After the Stop condition occurs,
the serial interface may immediately be re-enabled by
initiating a Start condition.
The HVC pin must be at VIHH until the completion of the
MTP Write Cycle (twc).
During an MTP write cycle, access to the volatile mem-
ory is allowed when using the appropriate command
sequence. Commands that address nonvolatile memory
are ignored until the MTP Write Cycle (twc) completes.
This allows the Host controller to operate on the Volatile
DAC registers.
Once a write command to a nonvolatile memory
location has been received, no other commands should
be received before the Stop condition occurs.
Writes to a NV memory location while an MTP write
cycle is occurring will force an error condition (A). A
Start bit is required to reset the command state
machine.
Figure 7-1 shows the waveform for a single write.
FIGURE 7-1:
Write Random Address Command.
Note:
Writes to MTP memory require the HVC
pin at 7.5V. This is not the normal operat-
ing conditions of the device; it is designed
for factory programming of configuration
parameters.
Note:
If a Stop condition does not occur, then the
NV Write does not occur and all following
command(s) will have an error condition
(A). A Start bit is required to reset the com-
mand state machine.
Memory Address
I2C ACK bit(1)
Note 1: The Acknowledge bit is generated by the MCP47CXBXX.
2: At the rising edge of the SCL signal for the last bit (D00) of the write command, the device updates the
value of the specified device register. For DAC Output registers, the output voltage depends on the
state of the LAT pin.
3: This command sequence does not need to terminate (using the Stop bit) and the write command can
be repeated (see continuous write format, Section 7.5.4 “Continuous Writes to Volatile Memory”).
SA
6
S
SA
5
SA
4
SA
3
SA
2
SA
1
SA
0
0
0
A
AD
4
AD
3
AD
2
AD
1
AD
0
0
0
x
A
AD
n
D
15
D
14
D
13
D
12
D
11
D
10
D
09
D
08
D
07
D
06
D
05
D
04
D
03
D
02
D
01
D
00
A
P
A
A
P
S
x
SA
n
0
0
I2C Start Bit
I2C Slave Address
I2C Write Bit
Write Command
Reserved, should be Set to ‘0’
I2C Stop Bit(3)
D
nn Register Data (to be written)
(2)
Control Byte
Write Command
Data to Write MSB
Data to Write LSB
Legend:



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