MCP47CMB21 datasheet(74/124 Pages) MICROCHIP

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MCP47CXBXX

DS20006089B-page 74

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7.3

General Call Commands

The general call commands utilize the I2C specification

reserved general call command address and command

codes. The General Call Reset command format is

specified by the “NXP I2C Specification”. The general

call wake-up command is a Microchip-defined format.

I2C devices Acknowledge the general call address

command (0x00 in the first byte). The meaning of the

general call address is always specified in the second

byte. The I2C specification does not allow ‘00000000’

(00h) in the second byte. Also, the ‘00000100’ and

‘00000110’ functionality is defined by the “NXP I2C

Specification”. Lastly, a data byte with a ‘1’ in the LSb

indicates a “Hardware General Call”.

Please refer to the “NXP I2C Specification” for more

details on the general call specifications.

The MCP47CXBXX devices support the following I2C

general calls:

• General Call Reset

• General Call Wake-up

See Section 7.7.1 “General Call Reset” for a full

description of the General Call Reset command and

the general call wake-up command.

7.4

Aborting a Transmission

A Restart or Stop condition in an expected data bit

position will abort the current command sequence, and

if the command is a write, that data word will not be writ-

ten to the MCP47CXBXX. Also, the I2C state machine

will be reset.

7.5

Write Command

The write command can be issued to both the volatile

and nonvolatile memory locations. Write commands

can also be structured as either single or continuous.

The continuous format allows the fastest data update

rate for the device’s memory locations.

The format of the command is shown in Figure 7-1. The

MCP47CXBXX generates the A/A bits. The format of

the command is shown in Figure 7-1 (single) and

Figure 7-3 (continuous); for example, ACK/NACK

behavior (see Figure 7-2).

A write command to a volatile memory location

changes that location after a properly formatted write

command and the rising edge of the D00 bit (last data

bit) clock has been detected.

A write command to a nonvolatile memory location will

only start a write cycle after a properly formatted write

command has been received and the Stop condition

has occurred.

7.5.1

SINGLE WRITE TO VOLATILE

MEMORY

For volatile memory locations, data are written to the

MCP47CXBXX after every data word transfer (16 bits)

during the rising edge of the last data bit. If a Stop or

Restart condition is generated during a data transfer

(before the last data bit is received), the data will not be

written to the MCP47CXBXX. After the A bit, the Master

can initiate the next sequence with a Stop or Restart

condition. (See Figure 7-1 for the write sequence.)

7.5.2

SINGLE WRITE TO NONVOLATILE

MEMORY (HVC PIN = VIL OR VIH)

In normal user mode, the MTP memory address

cannot be written. Writing to the MTP address space,

while the HVC pin is not at VIHH, will not have any

effect; the command is Acknowledged but the memory

is not modified.

Note 1: Writes to volatile memory locations will

be dependent on the state of their

respective WiperLock Technology bits.

2: During device communication, if the

device address/command combination is

invalid or an unimplemented device

address is specified, then the MCP47CX-

BXX will NACK that byte. To reset the I2C

state machine, the I2C communication

must detect a Start bit.

3: Writes to volatile memory locations will

be dependent on the state of their

respective WiperLock Technology bits.

Note:

Writes to a Volatile DAC register will not

transfer to the output register until the LAT

(HVC) pin is transitioned to the VIL

voltage.

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