MCS11 datasheet(21/108 Pages) PADAUK

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MCS11

ADC-Type Enhanced FPPA

TM Controller

Page 21 of 108

PDK-DS-MCS11_v020 – Apr. 20, 2018

5. Functional Description

5-1. Processing Units

There are eight processing units (FPP unit) inside the MCS11. In every processing unit, it includes (i) its own

Program Counter to control the program execution sequence (ii) its own Stack Pointer to store or restore the

program counter for program execution (iii) its own accumulator (iv) Status Flag to record the status of program

execution. Each FPP unit has its own program counter and accumulator for program execution, flag register to

record the status, and stack pointer for jump operation. Based on such architecture, FPP unit can execute its

own program independently, thus parallel processing can be expected.

These eight FPP units share the same 4Kx16 bits OTP user program memory, 208 bytes data SRAM and all

the IO ports, these eight FPP units are operated at mutual exclusive clock cycles to avoid interference. One

task switch is built inside the chip to decide which FPP unit should be active for the corresponding cycle. The

hardware diagram of processing units is illustrated in Fig. 5-1-1.

Fig. 5-1-1 Hardware Diagram of Processing units

These eight FPP units are operated at mutual exclusive clock cycles and can be enabled independently. The

system performance is shared to the assigned FPP units via pmode command; please refer to the description

of pmode instruction. The bandwidth assignment is nothing to do with FPP enable, means that the bandwidth

is also allocated to the assigned FPP unit even though it is disabled.

Program Counter 0

Stack Pointer 0

Accumulator 0

Flag register 0

FPP0

Program Counter 1

Stack Pointer 1

Accumulator 1

Flag register 1

FPP1

4KW OTP

User

Program

Memory

208 bytes

SRAM

IO Port

Task Switch

Program Counter 7

Stack Pointer 7

Accumulator 7

Flag register 7

FPP7

Hardware

Modules

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