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MCS11 Datasheet(PDF) 39 Page - PADAUK Technology. |
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MCS11 Datasheet(HTML) 39 Page - PADAUK Technology. |
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39 / 108 page  MCS11 ADC-Type Enhanced FPPA TM Controller ©Copyright 2018, PADAUK Technology Co. Ltd Page 39 of 108 PDK-DS-MCS11_v020 – Apr. 20, 2018 5-9. 8-bit Timer (Timer2) One 8-bit hardware timer (Timer2) is implemented in the MCS11; please refer to Fig. 5-9-1, shown its hardware diagram. The clock sources of Timer2 may come from system clock (CLK), internal high RC oscillator (IHRC), internal low RC oscillator (ILRC), PA0, PB0 and PA4, bit [7:4] of register tm2c is used to select the clock source of Timer2. If IHRC is selected as the clock source, the clock signal sent to Timer2 will keep running when using ICE in halt state. A clock pre-scaling module is provided with divided-by-1, 4, 16, and 64 options, controlled by bit [6:5] of tm2s register; one scaling module with divided-by-1~31 is also provided and controlled by bit [4:0] of tm2s register. In conjunction of pre-scaling function and scaling function, the frequency of Timer2 clock (TM2_CLK) can be wide range and flexible. The Timer2 counter performs 8-bit up-counting operation only; the 8-bit counter will be clear to zero and generate interrupt request automatically whenever its values reach to that of bound register tm2b, the bound register is used to define the period of Timer2. The timing diagram of Timer2 is shown in Fig.5-9-2. Fig. 5-9-1 Timer2 hardware diagram Fig. 5-9-2 Timing diagram of Timer2 M U X tm2c[7:4] CLK, IHRC, ILRC, PA0, ~PA0, PB0, ~PB0, PA4, ~PA4 Pre- scalar ÷ 1, 4, 16, 64 tm2s[6:5] Scalar ÷ 1 ~ 31 tm2s[4:0] 8-bit up counter Bound register tm2b[7:0] To request interrupt M U X tm2c[7:4] CLK, IHRC, ILRC, PA0, ~PA0, PB0, ~PB0, PA4, ~PA4 Pre- scalar ÷ 1, 4, 16, 64 tm2s[6:5] Scalar ÷ 1 ~ 31 tm2s[4:0] 8-bit up counter Bound register tm2b[7:0] To request interrupt Time Counter 0xFF Bound values Time out and Interrupt request 0x00 Time Counter 0xFF Bound values Time out and Interrupt request 0x00 |
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