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ADSP21486KSWZ3ABRL Datasheet(PDF) 36 Page - Analog Devices |
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ADSP21486KSWZ3ABRL Datasheet(HTML) 36 Page - Analog Devices |
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36 / 71 page  Rev. H | Page 36 of 71 | February 2020 ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489 Serial Ports In slave transmitter mode and master receiver mode, the maxi- mum serial port frequency is fPCLK/8. In master transmitter mode and slave receiver mode, the maximum serial port clock frequency is fPCLK/4. To determine whether communication is possible between two devices at clock speed n, the following specifications must be confirmed: 1) frame sync delay and frame sync setup and hold; 2) data delay and data setup and hold; and 3) SCLK width. Serial port signals (SCLK, frame sync, Data Channel A, Data Channel B) are routed to the DAI_P20–1 pins using the SRU. Therefore, the timing specifications provided below are valid at the DAI_P20–1 pins. Table 33. Serial Ports—External Clock Parameter Min Max Unit Timing Requirements tSFSE 1 Frame Sync Setup Before SCLK (Externally Generated Frame Sync in either Transmit or Receive Mode) 2.5 ns tHFSE 1 Frame Sync Hold After SCLK (Externally Generated Frame Sync in either Transmit or Receive Mode) 2.5 ns tSDRE 1 Receive Data Setup Before Receive SCLK 1.9 ns tHDRE 1 Receive Data Hold After SCLK 2.5 ns tSCLKW SCLK Width (tPCLK × 4) ÷ 2 – 1.5 ns tSCLK SCLK Period tPCLK × 4 ns Switching Characteristics tDFSE 2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in either Transmit or Receive Mode) 10.25 ns tHOFSE 2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in either Transmit or Receive Mode) 2 ns tDDTE 2 Transmit Data Delay After Transmit SCLK 9 ns tHDTE 2 Transmit Data Hold After Transmit SCLK 2 ns 1 Referenced to sample edge. 2 Referenced to drive edge. Table 34. Serial Ports—Internal Clock Parameter Min Max Unit Timing Requirements tSFSI 1 Frame Sync Setup Before SCLK (Externally Generated Frame Sync in either Transmit or Receive Mode) 7 ns tHFSI 1 Frame Sync Hold After SCLK (Externally Generated Frame Sync in either Transmit or Receive Mode) 2.5 ns tSDRI 1 Receive Data Setup Before SCLK 7 ns tHDRI 1 Receive Data Hold After SCLK 2.5 ns Switching Characteristics tDFSI 2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Transmit Mode) 4 ns tHOFSI 2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Transmit Mode) –1 ns tDFSIR 2 Frame Sync Delay After SCLK (Internally Generated Frame Sync in Receive Mode) 9.75 ns tHOFSIR 2 Frame Sync Hold After SCLK (Internally Generated Frame Sync in Receive Mode) –1 ns tDDTI 2 Transmit Data Delay After SCLK 3.25 ns tHDTI 2 Transmit Data Hold After SCLK –2 ns tSCKLIW Transmit or Receive SCLK Width 2 × tPCLK – 1.5 2 × tPCLK + 1.5 ns 1 Referenced to the sample edge. 2 Referenced to drive edge. |
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