ADSP21486KSWZ3ABRL datasheet(45/71 Pages) AD

45 / 71 page

ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489

Rev. H

Page 45 of 71

February 2020

Pulse-Width Modulation Generators (PWM)

The following timing specifications apply when the

ADDR23–8/DPI_14–1 pins are configured as PWM.

S/PDIF Transmitter

Serial data input to the S/PDIF transmitter can be formatted as

left-justified, I2S, or right-justified with word widths of 16, 18,

20, or 24 bits. The following sections provide timing for the

transmitter.

S/PDIF Transmitter-Serial Input Waveforms

Figure 29 shows the right-justified mode. Frame sync is high for

the left channel and low for the right channel. Data is valid on

the rising edge of serial clock. The MSB is delayed the minimum

in 24-bit output mode or the maximum in 16-bit output mode

from a frame sync transition, so that when there are 64 serial

clock periods per frame sync period, the LSB of the data is right-

justified to the next frame sync transition.

Table 42. Pulse-Width Modulation (PWM) Timing

Parameter

Min

Max

Unit

Switching Characteristics

tPWMW

PWM Output Pulse Width

tPCLK – 2

(216 – 2) × tPCLK

tPWMP

PWM Output Period

2 × tPCLK – 1.5

(216 – 1) × tPCLK

Figure 28. PWM Timing

PWM

OUTPUTS

tPWMW

tPWMP

Table 43. S/PDIF Transmitter Right-Justified Mode

Parameter

Nominal

Unit

Timing Requirement

tRJD

Frame Sync to MSB Delay in Right-Justified Mode

16-Bit Word Mode

18-Bit Word Mode

20-Bit Word Mode

24-Bit Word Mode

SCLK

Figure 29. Right-Justified Mode

MSB

LEFT/RIGHT CHANNEL

LSB

MSB–1 MSB–2

LSB+2

LSB+1

DAI_P20–1

SCLK

DAI_P20–1

SDATA

tRJD

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