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ADSP21486KSWZ3ABRL Datasheet(PDF) 56 Page - Analog Devices

Part # ADSP21486KSWZ3ABRL
Description  SHARC Processor
PDF  71 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP21486KSWZ3ABRL Datasheet(HTML) 56 Page - Analog Devices

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Rev. H
|
Page 56 of 71
|
February 2020
ADSP-21483/ADSP-21486/ADSP-21487/ADSP-21488/ADSP-21489
THERMAL CHARACTERISTICS
The ADSP-2148x processor is rated for performance over the
temperature range specified in Operating Conditions on
Page 18.
The JESD51 package thermal characteristics in this section are
provided for package comparison and estimation purposes only.
They are not intended for accurate system temperature calcula-
tion. System thermal simulation is required for accurate
temperature analysis that accounts for all specific 3D system
design features, including, but not limited to other heat sources,
use of heat-sinks, and the system enclosure. Contact Analog
Devices for package thermal models that are intended for use
with thermal simulation tools.
In Table 55, Table 56, and Table 57, airflow measurements com-
ply with JEDEC standards JESD51-2 and JESD51-6, and the
junction-to-board measurement complies with JESD51-8. Test
board design complies with JEDEC standards JESD51-7 (LQF-
P_EP). The junction-to-case measurement complies with MIL-
STD-883. All measurements use a 2S2P JEDEC test board.
To estimate the junction temperature of a single device while on
a JEDEC 2S2P PCB, use:
where:
TJ = junction temperature °C
TCASE = case temperature (°C) measured at the top center of the
package
JT = junction-to-top (of package) characterization parameter
is the typical value from Table 55, Table 56, and Table 57.
PD = power dissipation
Values of JA are provided for package comparison and PCB
design considerations. JA can be used for a first-order approxi-
mation of TJ by the equation:
where:
TA = ambient temperature °C
Figure 44. Typical Output Rise/Fall Time (20% to 80%, VDD_EXT = Min)
Figure 45. Typical Output Rise/Fall Delay (VDD_EXT = Max)
Figure 46. Typical Output Rise/Fall Delay (VDD_EXT = Min)
LOAD CAPACITANCE (pF)
6
0
0
10
4
2
25
200
150
50
75
100
125
175
y = 0.0571x + 0.5558
y = 0.0278x + 0.3138
y = 0.0258x + 0.3684
TYPE A DRIVE FALL
TYPE A DRIVE RISE
TYPE B DRIVE RISE
TYPE B DRIVE FALL
8
12
14
y = 0.0747x + 0.5154
LOAD CAPACITANCE (pF)
3
0
3.5
2
1
0.5
1.5
2.5
y = 0.0152x + 1.7607
y = 0.0068x + 1.7614
y = 0.0196x + 1.2945
y = 0.0074x + 1.421
0
25
200
150
50
75
100
125
175
TYPE A DRIVE FALL
TYPE A DRIVE RISE
TYPE B DRIVE RISE
TYPE B DRIVE FALL
4
4.5
LOAD CAPACITANCE (pF)
6
0
0
7
4
2
1
3
125
200
100
25
175
50
75
150
5
y = 0.0256x + 3.5859
y = 0.0116x + 3.5697
8
y = 0.0359x + 2.924
9
y = 0.0136x + 3.1135
TYPE A DRIVE FALL
TYPE A DRIVE RISE
TYPE B DRIVE FALL
TYPE B DRIVE RISE
T
J
T
CASE
JT
P
D

+
=
T
J
T
A
JA
P
D

+
=



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