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UM2179 Datasheet(PDF) 42 Page - STMicroelectronics |
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UM2179 Datasheet(HTML) 42 Page - STMicroelectronics |
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42 / 48 page ![]() Hardware layout and configuration UM2179 42/48 UM2179 Rev 9 5.17 Bootloader limitation 5.17.1 Bootloader operation Boot from system Flash memory runs bootloader code stored in the system Flash memory protected against writing and erasing. This allows in-system programming (ISP) with flashing of the STM32 user Flash memory. It also allows writing data into the RAM. The data is written via the USART, SPI, I2C, USB or CAN communication interface. 31 PH1 32 PA4 31 PB3 32 AGND 33 VBAT 34 PB0 33 PA10 34 PC4 35 PC2 36 PC1 35 PA2 36 PF5 37 PC3 38 PC0 37 PA3 38 PF4 39 PD4 40 PD3 39 GND 40 PE8 41 PD5 42 PG2 41 PD13 42 PF10 43 PD6 44 PG3 43 PD12 44 PE7 45 PD7 46 PE2 45 PD11 46 PD14 47 PE3 48 PE4 47 PE10 48 PD15 49 GND 50 PE5 49 PE12 50 PF14 51 PF1 52 PF2 51 PE14 52 PE9 53 PF0 54 PF8 53 PE15 54 GND 55 PD1 56 PF9 55 PE13 56 PE11 57 PD0 58 PG1 57 PF13 58 PF3 59 PG0 60 GND 59 PF12 60 PF15 61 PE1 62 PE6 61 PG14 62 PF11 63 PG9 64 PG15(5) 63 GND 64 PE0 65 PG12 66 PG10 65 PD10 66 PG8 67 - 68PG1367 PG7 68 PG5 69 PD9 70 PG11 69 PG4 70 PG6 1. Default state of BOOT0 is 0. It can be set to 1 when a jumper is plugged on the pins 5-7 of CN11. 2. VREF+ is not connected to CN12 by default. 3. U5V is the +5V power signal, coming from the ST-LINK/V2-1 USB connector. It rises before the +5V signal of the board. 4. PA13 and PA14 are shared with SWD signals connected to ST-LINK/V2-1. If ST-LINK part is not cut, it is not recommended to use them as I/O pins. 5. PB11 and PG15 are not available on the ‘-P’ suffixed boards. Table 12. ST morpho connector pin assignments (continued) CN11 odd pins CN11 even pins CN12 odd pins CN12 even pins Pin Pin name Pin Pin name Pin Pin name Pin Pin name |
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