HD404816FS datasheet(25/100 Pages) RENESAS

25 / 100 page

HD404818 Series

Interrupt Enable Flag (IE: $000, Bit 0): The interrupt enable flag enables/disables interrupt requests

(table 4). It is reset by an interrupt and set by the RTNI instruction.

Table 4 Interrupt Enable Flag

Interrupt Enabled/Disabled

Disabled

Enabled

External Interrupts (

INT

0, INT1):

The external interrupt request inputs (

INT

0, INT1) can be selected by

port mode register A (PMRA: $004).

The external interrupt request flags (IF0, IF1) are set at the falling edge of

INT

and

INT

1 inputs,

respectively (table 5).

The

INT

1 input can be used as a clock signal input to timer B, in which timer B counts up at each falling

edge of the

INT

1 input. When using INT1 as the timer B external event input, the external interrupt mask

(IM1) has to be set so that the interrupt request by

INT

1 will not be accepted (table 6).

More than two instruction cycle times (2t

cyc/2tsubcyc) are needed to detect the edge of INT0 or INT1.

External Interrupt Request Flags (IF0: $000, Bit 2; IF1: $001, Bit 0): The external interrupt request

flags (IF0, IF1) are set at the falling edge of the

INT

0 and INT1 inputs, respectively (table 5).

Table 5 External Interrupt Request Flags

IF0, IF1

Interrupt Request

0No

Yes

External Interrupt Masks (IM0: $000, Bit 3; IM1: $001, Bit 1): The external interrupt masks mask the

external interrupt requests (table 6).

Table 6 External Interrupt Masks

IM0, IM1

Interrupt Request

Enabled

Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $001, Bit 2): The timer A interrupt request flag is set by the

overflow output of timer A (table 7).

HD404816FS Datasheet(PDF) 25 Page - Renesas Technology Corp

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