TMS320F28075PZPQ datasheet(70/196 Pages) TI

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Wake-up

Signal

OSCCLK

XCLKOUT

Flushing Pipeline

(A)

Device

Status

STANDBY

Normal Execution

STANDBY

(G)

(B)

(C)

(D)(E)

(F)

d(IDLE-XCOS)

w(WAKE-INT)

d(WAKE-STBY)

TMS320F28076, TMS320F28075

SPRS902I – OCTOBER 2014 – REVISED JUNE 2020

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Product Folder Links: TMS320F28076 TMS320F28075

Specifications

IDLE instruction is executed to put the device into STANDBY mode.

The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before

being turned off. This delay enables the CPU pipeline and any other pending operations to flush properly.

Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in

STANDBY mode. After the IDLE instruction is executed, a delay of five OSCCLK cycles (minimum) is needed before

the wake-up signal could be asserted.

The external wake-up signal is driven active.

The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement.

Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wakeup behavior of the

device will not be deterministic and the device may not exit low-power mode for subsequent wakeup pulses.

After a latency period, the STANDBY mode is exited.

Normal execution resumes. The device will respond to the interrupt (if enabled).

Figure 5-18. STANDBY Entry and Exit Timing Diagram

TMS320F28075PZPQ Datasheet(PDF) 70 Page - Texas Instruments