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TMS320F28075PZPQ Datasheet(PDF) 13 Page - Texas Instruments

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Part # TMS320F28075PZPQ
Description  TMS320F2807x Microcontrollers
PDF  196 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS320F28075PZPQ Datasheet(HTML) 13 Page - Texas Instruments

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TMS320F28076, TMS320F28075
www.ti.com
SPRS902I – OCTOBER 2014 – REVISED JUNE 2020
Submit Documentation Feedback
Product Folder Links: TMS320F28076 TMS320F28075
Terminal Configuration and Functions
Copyright © 2014–2020, Texas Instruments Incorporated
4.2
Signal Descriptions
Table 4-1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned.
The peripheral signals that are listed under them are alternate functions. Some peripheral functions may
not be available in all devices. See Table 3-1 for details. All GPIO pins are I/O/Z and have an internal
pullup, which can be selectively enabled or disabled on a per-pin basis. This feature only applies to the
GPIO pins. The pullups are not enabled at reset.
Table 4-1. Signal Descriptions
TERMINAL
I/O/Z(1)
DESCRIPTION
NAME
MUX
POSITION
PTP
PIN
NO.
PZP
PIN
NO.
ADC, DAC, AND COMPARATOR SIGNALS
VREFHIA
37
19
I
ADC-A high reference. This voltage must be driven into the
pin from external circuitry. Place at least a 1-µF capacitor on
this pin. This capacitor should be placed as close to the
device as possible between the VREFHIA and VREFLOA pins.
NOTE: Do not load this pin externally.
VREFHIB
53
37
I
ADC-B high reference. This voltage must be driven into the
pin from external circuitry. Place at least a 1-µF capacitor on
this pin. This capacitor should be placed as close to the
device as possible between the VREFHIB and VREFLOB pins.
NOTE: Do not load this pin externally.
VREFHID
55
–
I
ADC-D high reference. This voltage must be driven into the
pin from external circuitry. Place at least a 1-µF capacitor on
this pin. This capacitor should be placed as close to the
device as possible between the VREFHID and VREFLOD pins.
NOTE: Do not load this pin externally.
VREFLOA
33
17
I
ADC-A low reference.
On the PZP package, pin 17 is double-bonded to VSSA and
VREFLOA. On the PZP package, pin 17 must be connected to
VSSA on the system board.
VREFLOB
50
34
I
ADC-B low reference
VREFLOD
51
–
I
ADC-D low reference
ADCIN14
44
26
I
Input 14 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all ADCs
together from an external reference.
CMPIN4P
I
Comparator 4 positive input
ADCIN15
45
27
I
Input 15 to all ADCs. This pin can be used as a general-
purpose ADCIN pin or it can be used to calibrate all ADCs
together from an external reference.
CMPIN4N
I
Comparator 4 negative input
ADCINA0
43
25
I
ADC-A input 0. There is a 50-kΩ internal pulldown on this pin
in both an ADC input or DAC output mode which cannot be
disabled.
DACOUTA
O
DAC-A output
ADCINA1
42
24
I
ADC-A input 1. There is a 50-kΩ internal pulldown on this pin
in both an ADC input or DAC output mode which cannot be
disabled.
DACOUTB
O
DAC-B output
ADCINA2
41
23
I
ADC-A input 2
CMPIN1P
I
Comparator 1 positive input
ADCINA3
40
22
I
ADC-A input 3
CMPIN1N
I
Comparator 1 negative input
ADCINA4
39
21
I
ADC-A input 4
CMPIN2P
I
Comparator 2 positive input
ADCINA5
38
20
I
ADC-A input 5
CMPIN2N
I
Comparator 2 negative input



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