AM6421 datasheet(155/237 Pages) TI

155 / 237 page

7.10.5.8.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode

NO.

PARAMETER

DESCRIPTION

MODE

(15)

MIN

MAX

UNIT

133 MHz

tR(d)

Rise time, output data GPMC_AD[15:0]

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.00

tF(d)

Fall time, output data GPMC_AD[15:0]

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.00

FA0

tw(be[x]nV)

Pulse duration, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid time

Read

0+N (12)

Write

0+N (12)

FA1

tw(csnV)

Pulse duration, output chip select GPMC_CSn[i](13)

low

Read

0+A (1)

Write

0+A (1)

FA3

td(csnV-advnIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE invalid

Read

-2+B (2)

2+B (2)

Write

-2+B (2)

2+B (2)

FA4

td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn invalid

(Single read)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+C (3)

2+C (3)

FA9

td(aV-csnV)

Delay time, output address GPMC_A[27:1] valid to

output chip select GPMC_CSn[i](13) valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+J (9)

2+J (9)

FA10 td(be[x]nV-csnV)

Delay time, output lower-byte enable and

command latch enable GPMC_BE0n_CLE, output

upper-byte enable GPMC_BE1n valid to output

chip select GPMC_CSn[i](13) valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+J (9)

2+J (9)

FA12 td(csnV-advnV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output address valid and address latch

enable GPMC_ADVn_ALE valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+K (10)

2+K (10)

FA13 td(csnV-oenV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+L (11)

2+L (11)

FA16 tw(aIV)

Pulse duration output address GPMC_A[26:1]

invalid between 2 successive read and write

accesses

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

0+G (7)

FA18 td(csnV-oenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output enable GPMC_OEn_REn invalid

(Burst read)

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+I (8)

2+I (8)

FA20 tw(aV)

Pulse duration, output address GPMC_A[27:1]

valid - 2nd, 3rd, and 4th accesses

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

0+D (4)

FA25 td(csnV-wenV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output write enable GPMC_WEn valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+E (5)

2+E (5)

FA27 td(csnV-wenIV)

Delay time, output chip select GPMC_CSn[i](13)

valid to output write enable GPMC_WEn invalid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+F (6)

2+F (6)

FA28 td(wenV-dV)

Delay time, output write enable GPMC_WEn valid

to output data GPMC_AD[15:0] valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

2.00

FA29 td(dV-csnV)

Delay time, output data GPMC_AD[15:0] valid to

output chip select GPMC_CSn[i](13) valid

div_by_1_mode;

GPMC_FCLK_MUX;

TIMEPARAGRANULARITY_X1

-2+J (9)

2+J (9)

www.ti.com

AM6442, AM6441, AM6421

AM6412, AM6411

SPRSP56 – JANUARY 2021

Submit Document Feedback

155

Product Folder Links: AM6442 AM6441 AM6421 AM6412 AM6411

AM6421 Datasheet(PDF) 155 Page - Texas Instruments

AM6421 Datasheet(HTML) 155 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL