DWM3000 Datasheet

© Qorvo 2020

Preliminary

Version 0.1

Page 4

The DWM3000 module is an IEEE 802.15.4-2011 and IEEE 802.15.4z (BPRF mode) UWB implementation. RF

components, Decawave DW3110 UWB transceiver, and other components reside on-module. DWM3000

enables cost effective and reduced complexity integration of UWB communications and ranging features, greatly

accelerating design implementation.

1.1 DWM3000 Functional Description

The DW3110 on board the DWM3000 is a fully integrated low-power, single chip CMOS RF transceiver IC. The

DWM3000 module requires no RF design as the antenna and associated analog and RF components are on the

module.

The module contains an on-board 38.4 MHz reference crystal. The crystal has been trimmed in production to

reduce the initial frequency error to approximately 2 ppm, using the DW3110 IC’s internal on-chip crystal trimming

circuit, see section 2.1.1.

Always-On (AON) memory can be used to retain DWM3000 configuration data during the lowest power operational

states when the on-chip voltage regulators are disabled. This data is uploaded and downloaded automatically. Use

of DWM3000 AON memory is configurable.

The on-chip voltage and temperature monitors allow the host to read the voltage on the VDD1 pin and the internal

die temperature information from the DW3110.

See the DW3000 datasheet for more detailed information on device functionality, electrical specifications and

typical performance.

1.2 DWM3000 Power Up

DWM3000 is designed such that it can be powered in a number of different configurations depending on the

application. These options are described below. Figure 1 shows the power up sequence when external power

sources are applied. The power supply design should ensure that VDD2a/b and VDD3 are stable less than 10ms

after VDD1 (3.3V) comes up, otherwise a device reset is required.

When the external power source is applied to the DWM3000 for the first time (cold power up), the internal Power

On Reset (POR) circuit compares the externally applied supply voltage (VDD1) to an internal power-on threshold

(approximately 1.5V), and once this threshold is passed the AON block is released from reset and the external

device enable pin EXTON is asserted.

Then the VDD2a/b and VDD3 supplies are monitored and once they are above the required voltage as specified

in the datasheet (2.2V and 1.4V respectively), the fast RC oscillator (FAST_RC) and crystal (XTAL Oscillator) will

come on within 500 µs and 1 ms respectively.

The DWM3000 digital core will be held in reset until the crystal oscillator is stable. Once the digital reset is de-

asserted the digital core wakes up and enters the INIT_RC state, (see Figure 1 and Figure 2). Then once the

configurations stored in AON and OTP have been restored (into the configuration registers) the device will enter

IDLE_RC. Then the host can set the AINIT2IDLE configuration bit in SEQ_CTRL and the IC will enable the

CLKPLL and wait for it to lock before entering the IDLE_PLL state.