DWM3000 Datasheet

© Qorvo 2020

Preliminary

Version 0.1

Page 8

1.3.3 SPI Transaction Formatting

The SPI command structure allows for 4 different types of SPI command:

1. Fast, single byte commands. Up to 32 unique commands such as “TX now”, “TX/RX Off”.

2. Fast addressed mode. Allowing for read and write addressing to 32 master addresses. This command

structure is padded by a trailing bit to allow the SPI address decoder time to fetch any read data. The

length of the read is determined by the length of the SPI transaction.

3. Full addressed mode. Allowing for read and write addressing to 32 master addresses and up to 128 byte

offset addressing. This command structure is padded by a trailing bit to allow the SPI address decoder

time to fetch any read data. The length of the read or write is determined by the length of the SPI

transaction.

4. Masked write transaction. These are intended to simplify read-modify-write operations by allowing the

host to write to an address and apply a set, clear or toggle mask to 1, 2, or 4 bytes. The SPI command

decoder then carries out the required read-modify-write instructions internally.

Figure 7: SPI Command Formatting

RD

/

WR

8/

16

ADD

0

0

X octet data

2

3

4

5

6

7

1

8

9 10 11

13

12

0

16 17 18 19 20 21

15

22 23

14

M0

M1

1

X octet data

1/

0

0

0

1

1 octet AND mask

1

1

0

1

2 octet AND mask

1

0

1

1

4 octet AND mask

1

1

1

Masked write

transaction

Short addressed

transaction

1/

0

Full

addressed

transaction

byte0[5:1]

5-bit base address

Bit count

1

0

1

Fast Command

byte1[7:2]

sub-address [5:0]

byte0[5:1]

5-bit base address

byte1[7:2]

sub-address [5:0]

byte0[5:1]

5-bit base address

byte1[7:2]

sub-address [5:0]

byte0[5:1]

5-bit base address

byte0[5:1]

5-bit base address

Fast

command

transaction

Mode bits (M1, M0):

00 = RD/WR

01= WR: AND/OR 8-bit

10 = WR: AND/OR 16-bit

11 = WR: AND/OR 32-bit

1 octet OR mask

2 octet OR mask

4 octet OR mask

byte1[6:0]

7-bit sub-address

MSB

byte0

LSB

MSB

byte1

LSB

byte0[0]

sub-address [6]