TMS320F28075PZP datasheet(22/192 Pages) TI

22 / 192 page

TERMINAL

I/O/Z

(1)

DESCRIPTION

NAME

MUX

POSITION

PTP

NO.

PZP

NO.

GPIO92

0, 4, 8, 12

174

I/O

General-purpose input/output 92

EM1A19

External memory interface 1 address line 19

EM1BA1

External memory interface 1 bank address 1

SCLA

I/OD

I2C-A clock open-drain bidirectional port

GPIO93

0, 4, 8, 12

175

–

I/O

General-purpose input/output 93

EM1BA0

External memory interface 1 bank address 0

SCITXDD

SCI-D transmit data

GPIO94

0, 4, 8, 12

176

–

I/O

General-purpose input/output 94

SCIRXDD

SCI-D receive data

GPIO99

0, 4, 8, 12

I/O

General-purpose input/output 99

EQEP1I

I/O

Enhanced QEP1 index

GPIO133/AUXCLKIN

0, 4, 8, 12

118

–

I/O

General-purpose input/output 133. The AUXCLKIN function of

this GPIO pin could be used to provide a single-ended 3.3-V

level clock signal to the Auxiliary Phase-Locked Loop

(AUXPLL), whose output is used for the USB module. The

AUXCLKIN clock may also be used for the CAN module.

SD2_C2

Sigma-Delta 2 channel 2 clock input

RESET

XRS

124

I/OD

Device Reset (in) and Watchdog Reset (out). The devices

have a built-in power-on reset (POR) circuit. During a power-

on condition, this pin is driven low by the device. An external

circuit may also drive this pin to assert a device reset. This pin

is also driven low by the MCU when a watchdog reset or NMI

watchdog reset occurs. During watchdog reset, the XRS pin is

driven low for the watchdog reset duration of 512 OSCCLK

cycles. A resistor with a value from 2.2 kΩ to 10 kΩ should be

placed between XRS and VDDIO. If a capacitor is placed

between XRS and VSS for noise filtering, it should be 100 nF

or smaller. These values will allow the watchdog to properly

drive the XRS pin to VOL within 512 OSCCLK cycles when the

watchdog reset is asserted. The output buffer of this pin is an

open drain with an internal pullup. If this pin is driven by an

external device, it should be done using an open-drain device.

CLOCKS

123

On-chip crystal-oscillator input. To use this oscillator, a quartz

crystal must be connected across X1 and X2. If this pin is not

used, it must be tied to GND.

This pin can also be used to feed a single-ended 3.3-V level

clock. In this case, X2 is a No Connect (NC).

121

On-chip crystal-oscillator output. A quartz crystal may be

connected across X1 and X2. If X2 is not used, it must be left

unconnected.

TMS320F28076, TMS320F28075

SPRS902J – OCTOBER 2014 – REVISED FEBRUARY 2021

www.ti.com

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Product Folder Links: TMS320F28076 TMS320F28075

TMS320F28075PZP Datasheet(PDF) 22 Page - Texas Instruments

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