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AT90PWM2 Datasheet(PDF) 66 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 66 Page - ATMEL Corporation |
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66 / 365 page  66 AT90PWM2/3 4317B–AVR–02/05 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the suc- ceeding positive clock edge. As indicated by the two arrows t pd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion. When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 27. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay t pd through the synchronizer is 1 system clock period. Figure 27. Synchronization when Reading a Software Assigned Pin Value out PORTx, r16 nop in r17, PINx 0xFF 0x00 0xFF SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17 t pd |
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