ATMEGA640 datasheet(126/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

16.9 Register Description

16.9.1

TCCR0A – Timer/Counter Control Register A

• Bits 7:6 – COM0A1:0: Compare Match Output A Mode

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the

OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data

Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting.

Table 16-2 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode (non-

PWM).

Table 16-3 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.

Note:

1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is ignored,

but the set or clear is done at BOTTOM. See “Fast PWM Mode” on page 121 for more details.

Table 16-4 on page 127 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct

PWM mode.

Bit

0x24 (0x44)

COM0A1

COM0A0

COM0B1

COM0B0

–

WGM01

WGM00

TCCR0A

Read/Write

R/W

Initial Value

Table 16-2.

Compare Output Mode, non-PWM Mode

COM0A1

COM0A0

Description

Normal port operation, OC0A disconnected

Toggle OC0A on Compare Match

Clear OC0A on Compare Match

Set OC0A on Compare Match

Table 16-3.

Compare Output Mode, Fast PWM Mode(1)

COM0A1

COM0A0

Description

Normal port operation, OC0A disconnected

WGM02 = 0: Normal Port Operation, OC0A Disconnected

WGM02 = 1: Toggle OC0A on Compare Match

Clear OC0A on Compare Match, set OC0A at BOTTOM

(non-inverting mode)

Set OC0A on Compare Match, clear OC0A at BOTTOM

(inverting mode)

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