ATMEGA640 datasheet(140/436 Pages) MICROCHIP

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ATmega640/V-1280/V-1281/V-2560/V-2561/V [DATASHEET]

DS40002211A

17.6 Input Capture Unit

The Timer/Counter incorporates an input capture unit that can capture external events and give them a time-stamp

indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the

ICPn pin or alternatively, for the Timer/Counter1 only, via the Analog Comparator unit. The time-stamps can then

be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps

can be used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 17-3. The elements of the block diagram

that are not directly a part of the input capture unit are gray shaded. The small “n” in register and bit names indi-

cates the Timer/Counter number.

Figure 17-3. Input Capture Unit Block Diagram

Note:

The Analog Comparator Output (ACO) can only trigger the Timer/Counter1 ICP – not Timer/Counter3, 4 or 5.

When a change of the logic level (an event) occurs on the Input Capture Pin (ICPn), alternatively on the analog

Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be triggered.

When a capture is triggered, the 16-bit value of the counter (TCNTn) is written to the Input Capture Register

(ICRn). The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into ICRn

matically cleared when the interrupt is executed. Alternatively the ICFn flag can be cleared by software by writing a

logical one to its I/O bit location.

Reading the 16-bit value in the Input Capture Register (ICRn) is done by first reading the low byte (ICRnL) and

then the high byte (ICRnH). When the low byte is read the high byte is copied into the high byte Temporary Regis-

ter (TEMP). When the CPU reads the ICRnH I/O location it will access the TEMP Register.

The ICRn Register can only be written when using a Waveform Generation mode that utilizes the ICRn Register for

defining the counter’s TOP value. In these cases the Waveform Generation mode (WGMn3:0) bits must be set

before the TOP value can be written to the ICRn Register. When writing the ICRn Register the high byte must be

written to the ICRnH I/O location before the low byte is written to ICRnL.

For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers” on page 135.

ICFn (Int.Req.)

Analog

Comparator

WRITE

ICRn (16-bit Register)

ICRnH (8-bit)

Noise

Canceler

ICPn

Edge

Detector

TEMP (8-bit)

DATA BUS (8-bit)

ICRnL (8-bit)

TCNTn (16-bit Counter)

TCNTnH (8-bit)

TCNTnL (8-bit)

ACIC*

ICNC

ICES

ACO*

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