UPD301B datasheet(24/45 Pages) MICROCHIP

24 / 45 page

UPD301B/C

DS00003412A-page 24

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2020 Microchip Technology Inc.

4.3.8.1

FRS Sink Operation

When operating as a Sink, the device is configured to detect FRS signaling by setting FRS Detect Enable (FRS_DE-

T_EN) in FRS Control Register. The CC detection logic is programmed to detect three thresholds (SinkTxOK, Sink-

TXNG, FRSWAP) and samples each threshold in round robin fashion. The sampling rate is determined by CC Sample

Clock Register.

When a match is detected on FRSWAP threshold, the CC detection logic will “park” at this threshold and continue mon-

itoring the output of the comparator. While “parked” the output of the CC comparator will be sampled at an increased

rate of 12 MHz. This higher sampling rate will prevent PD messages from inadvertently looking like FRS signaling which

will happen on occasion when the sampling rate is similar or slower than the ~270 kbps rate of PD messages.

It will continue debouncing for the amount of time specified in FRS CC Debounce Register. The FRSWAP threshold is

indicated by FRS Threshold Select Register.

If the debounce is successful, then the FRS_RCV_STS interrupt is asserted and the CC detection logic resumes sam-

pling all enabled thresholds. If the FRS debounce fails, the CC detection logic resumes sampling all enabled thresholds.

In this mode of operation the CC Comparator operates at a faster rate in order to minimize the FRS detection latency.

This is enabled by placing this the comparator into a high bandwidth mode.

After detecting the FRS signaling, the “old Sink” must start supplying vSafe5V at USB Type-C™ current VBUS no later

than tSrcFRSwap (150 us) after VBUS has dropped below vSafe5V. This must be accomplished via circuitry external

to the device.

4.3.8.2

FRS Source Operation

The initial Source shall signal a FRS request by driving the CC pin to ground with a resistance of less than 5 Ohms for

a period defined by FRS Transmission Length Register. The FRS request signaling is initiated by either a CSR write or

GPIO assertion.

The former case is implemented by setting the FRS Request (FRS_REQ_EN) bit in FRS Control Register. This bit self

clears after the FRS request is transmitted. For the latter case, the PIO is selected by the FRS Request PIO

(FRS_REQ_PIO) field in FRS Control Register.

Transmission of FRS signaling will take precedence over PD MAC TX communication. The FRS PD resistor is enabled

in tandem on the CC pin determined by FRS CC Select (FRS_CC_SEL) in FRS Control Register. This configuration

remains until FRS transmission has completed.

4.3.8.3

Dead Battery (UPD301C Only)

The UPD301C device includes two variations of the Rd resistor implementation: Rd (Dead Battery) and Rd (Trimmed).

The CC pins are configured to present either Hi-Z or an untrimmed Rd pull-down resistance when connected to a DFP

advertising a pull-up resistance.

Figure 4-2 illustrates the configuration for supporting dead battery cases. The UFP pull-up activates the FET in series

with RD_DB and enables the untrimmed dead battery pull-down.

Note:

The upper threshold used for vSafe5V should be used for determining when VBUS has dropped below

vSafe5v to help meet tSrcFRSwap requirement.

Note:

Matching of a VBUS threshold may be selected as a source to a PIO override. Additionally, VBUS threshold

match ANDed with FRS signal detect may also be used as a PIO override source.

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