ADGS1408 datasheet(23/34 Pages) AD

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Data Sheet

ADGS1408/ADGS1409

Rev. 0 | Page 23 of 34

THEORY OF OPERATION

The ADGS1408/ADGS1409 are a set of serially controlled analog

multiplexers comprising eight single channels and four differential

channels, respectively, with error detection features. SPI Mode 0

and SPI Mode 3 can be used with the devices. The devices operate

with SCLK frequencies up to 50 MHz. The default mode for the

ADGS1408/ADGS1409 is address mode, in which the registers of

the device are accessed by a 16-bit SPI command bounded by

CS. The SPI command becomes 24-bit if the user enables CRC

error detection. Other error detection features include SCLK count

error and invalid read/write error. If any of these SPI interface

errors occur, they are detectable by reading the error flags

other modes, namely burst mode and daisy-chain mode.

The interface pins of the ADGS1408/ADGS1409 are CS, SCLK,

SDI, and SDO. Hold CS low when using the SPI interface. Data is

captured on SDI on the rising edge of SCLK, and data is propagated

out on SDO on the falling edge of SCLK. SDO has an open-drain

output. Connect a pull-up to this output. When not pulled low by

the ADGS1408/ADGS1409, SDO is in a high impedance state.

ADDRESS MODE

Address mode is the default mode for the ADGS1408/ADGS1409

on power-up. A single SPI frame in address mode is bounded by

a CS falling edge and the succeeding CS rising edge. An SPI frame

is comprised of 16 SCLK cycles. The timing diagram for address

mode is shown in Figure 45. The first SDI bit indicates if the SPI

command is a read or write command. When the first bit is set

to 0, a write command is issued, and if the first bit is set to 1, a

read command is issued. The next seven bits determine the target

addressed register. The last eight bits are ignored during a read

command, because during these clock cycles, SDO propagates out

the data contained in the addressed register.

The target register address of an SPI command is determined on

the eighth SCLK rising edge. Data from this register propagates out

on SDO from the 9th to the 16th SCLK falling edge during SPI

reads. A register write occurs on the 16th SCLK rising edge

during SPI writes.

During any SPI command, SDO sends out eight alignment bits

on the first eight SCLK falling edges. The alignment bits observed

at SDO are 0x25.

ERROR DETECTION FEATURES

Protocol and communication errors on the SPI interface are

detectable. There are three detectable errors: incorrect SCLK error

detection, invalid read and write address error detection, and

CRC error detection. Each error has a corresponding enable bit

in the error configuration register. In addition, there is an error

flag bit for each error in the error flags register.

CRC Error Detection

The CRC error detection feature extends a valid SPI frame by

eight SCLK cycles. These eight extra cycles are needed to send the

CRC byte for that SPI frame. The CRC byte is calculated by the SPI

block using the 16-bit payload: the R/W bit, Register Address

Bits[6:0], and Register Data Bits[7:0]. The CRC polynomial

used in the SPI block is x8 + x2 + x1 + 1 with a seed value of 0.

For a timing diagram with CRC enabled, see Figure 46. Register

writes occur at the 24th SCLK rising edge with CRC error

checking enabled.

During an SPI write, the microcontroller/CPU provides the

CRC byte through SDI. The SPI block checks the CRC byte just

before the 24th SCLK rising edge. On this same edge, the register

write is prevented if an incorrect CRC byte is received by the SPI

interface. In the case of the incorrect CRC byte being detected, the

CRC error flag is asserted in the error flags register.

During an SPI read, the CRC byte is provided to the micro-

controller through SDO.

The CRC error detection feature is disabled by default and can

be configured by the user through the error configuration register.

SDO

R/W

101112

131415

SDI

SCLK

Figure 45. Address Mode Timing Diagram

SDO

R/W

SDI

SCLK

Figure 46. Timing Diagram with CRC Enabled

ADGS1408 Datasheet(PDF) 23 Page - Analog Devices

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