MAX17843ACB datasheet(51/131 Pages) MAXIM

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UART Ports

Two UART ports are utilized, a lower port (RXL/TXL) and

an upper port (RXU/TXU). Each port consists of a differ-

ential line driver and differential line receiver. DC-blocking

capacitors or transformers can be used to isolate daisy-

chain devices that are operating at different common-

mode voltages. During communication, the character

encoding provides a balanced signal (50% duty cycle)

that ensures charge neutrality on the isolation capacitors.

UART Transmitter

When no data is being transmitted by the UART, the

differential outputs must be driven to a common level

to maintain a neutral charge difference between the

AC-coupling capacitors or to avoid saturation of the

isolation transformers. In the default idle mode (low-Z),

the transmitter drives both outputs to a logic-low level

to balance the charge on the capacitors; this also works

well with transformer coupling. The high-Z idle mode

(TXLHIZIDLE, TXUHIZIDLE = 1) places the TX pins in a

high-Z state in idle mode, which may be desirable to mini-

mize the effects of charging and discharging the isolation

capacitors. The idle mode for the upper and lower ports

can be controlled independently through the TXLHIZIDLE

and TXUHIZIDLE configuration bits.

UART Receiver

The UART receiver has a wide common-mode input

range to tolerate harsh EMC conditions, which can be

operated in differential mode or single-ended mode per

Table 21. By default, the UART receivers are configured

for differential mode. In single-ended mode, the RXP input

is grounded and the RXN input receives inverse data,

as described in the Applications Information section. In

single-ended mode, the receiver input threshold is nega-

tive so that a zero differential voltage (VRXP, VRXN = 0V)

is considered to be a logic-one and a negative differential

voltage (VRXN high) is a logic-zero.

UART RX Modes

During the first preamble received after a reset, the receiv-

er automatically detects if the received signal is single-

ended and if so, places the receiver in single-ended mode;

therefore, the device must be reset for any change in the

RX-mode hardware configuration to be detected.

The receiver mode is indicated by the ALRTCOMMSEL

bit (for lower port) and ALRTCOMMSEU bit (for upper

port) of the FMEA1 register, as shown in Table 21. If the

RXP input is open circuit, RX-mode detection places the

UART in single-ended mode so the port can still oper-

ate, albeit with reduced noise immunity. The host can

diagnose this condition by checking ALRTCOMMSEL and

ALRTCOMMSEU after any POR event. Any other faults

result in communication errors.

Figure 29. UART Transmitter

TX[U,L][P,N]

VDDL[2,3]

TX[U,L]IDLEHIZ

DRIVE LOW

DRIVE HIGH

GNDL[2,3]

ESD CLAMP

(UARTSTATE=IDLE?)

MAX17843

12-Channel, High-Voltage Smart Sensor

Data-Acquisition Interface

www.maximintegrated.com

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