ADRF6821 datasheet(51/61 Pages) AD

51 / 61 page

Data Sheet

ADRF6821

Rev. A | Page 51 of 61

Address: 0x120E, Reset: 0x04, Name: SYNTH_0

Referenc e Div ide by 2

1: Referenc e Div ide by 2 Enabled.

0: Referenc e Div ide by 2 Dis abled.

Referenc e Doubler Enable - Optionally

Double-Buffered

[ 7 :4 ] RES ERV ED

[ 0 ] RD IV 2 _S EL ( R/W )

[ 3 ] D O UBLER_EN ( R/W )

[ 2 :1 ] RES ERV ED

Table 60. Bit Descriptions for SYNTH_0

Bits

Bit Name

Settings

Description

Reset

Access

[7:4]

RESERVED

Reserved

0x0

DOUBLER_EN

Reference Doubler Enable—Optionally Double Buffered

0x0

R/W

[2:1]

RESERVED

Reserved

0x2

R/W

RDIV2_SEL

Reference Divide by 2

0x0

R/W

Reference Divide by 2 Disabled

Reference Divide by 2 Enabled

Address: 0x1214, Reset: 0x48, Name: MULTI_FUNC_SYNTH_CTRL_0214

Lock Detect Bias

11: 10uA.

10: 20uA.

01: 30uA.

00: 40uA.

Lock Detect Precision

011: Check 8192 Consecutive PFD Cycles.

010: Check 4096 Consecutive PFD Cycles.

001: Check 2048 Consecutive PFD Cycles.

000:

for Lock.

Check 1024 Consecutive PFD Cycles

[7:6] LD_BIAS (R/W)

[2:0] RESERVED

[5:3] LDP (R/W)

Table 61. Bit Descriptions for MULTI_FUNC_SYNTH_CTRL_0214

Bits

Bit Name

Settings

Description

Reset

Access

[7:6]

LD_BIAS

Lock Detect Bias

0x1

R/W

40 µA.

30 µA.

20 µA.

10 µA.

[5:3]

LDP

Lock Detect Precision

0x1

R/W

000

Check 1024 Consecutive PFD Cycles for Lock.

001

Check 2048 Consecutive PFD Cycles.

010

Check 4096 Consecutive PFD Cycles.

011

Check 8192 Consecutive PFD Cycles.

[2:0]

RESERVED

Reserved.

0x0

R/W

Address: 0x1215, Reset: 0x00, Name: SI_BAND_0

Manually Pr o g r am m e d VCO Band

[ 7 : 0 ] S I_BAN D _S EL ( R/W )

Table 62. Bit Descriptions for SI_BAND_0

Bits

Bit Name

Settings

Description

Reset

Access

[7:0]

SI_BAND_SEL

Manually Programmed VCO Band.

0x0

R/W

ADRF6821 Datasheet(PDF) 51 Page - Analog Devices

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