STM32H723VG datasheet(128/227 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32H723xE/G

128/227

DS13313 Rev 2

Figure 18. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 50. Otherwise the reset is not taken into account by the device.

6.3.18

FMC characteristics

Unless otherwise specified, the parameters given in Table 57 to Table 70 for the FMC

interface are derived from tests performed under the ambient temperature, fHCLK frequency

and VDD supply voltage conditions summarized in Table 12: General operating conditions,

with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Measurement points are done at CMOS levels: 0.5VDD

•

IO Compensation cell activated.

•

HSLV activated when VDD ≤ 2.7 V

•

VOS level set to VOS0.

Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics.

Asynchronous waveforms and timings

Figure 19 through Figure 21 represent asynchronous waveforms and Table 57 through

Table 64 provide the corresponding timings. The results shown in these tables are obtained

with the following FMC configuration:

•

AddressSetupTime = 0x1

•

AddressHoldTime = 0x1

•

DataSetupTime = 0x1 (except for asynchronous NWAIT mode , DataSetupTime = 0x5)

•

BusTurnAroundDuration = 0x0

•

Capacitive load CL = 30 pF

In all timing tables, the TKERCK is the fmc_ker_ck clock period.

ai14132d

STM32

RPU

NRST(2)

VDD

Filter

Internal Reset

0.1 μF

External

reset circuit (1)

STM32H723VG Datasheet(PDF) 128 Page - STMicroelectronics

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