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STM32H723VG Datasheet(PDF) 127 Page - STMicroelectronics |
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STM32H723VG Datasheet(HTML) 127 Page - STMicroelectronics |
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127 / 227 page ![]() DS13313 Rev 2 127/227 STM32H723xE/G Electrical characteristics 208 Analog switch between ports Pxy_C and Pxy PA0_C, PA1_C, PC2_C and PC3_C can be connected internally to PA0, PA1, PC2 and PC3, respectively (refer to SYSCFG_PMCR register in RM0468 reference manual). The switch is controlled by VDDSWITCH voltage level. It is defined through BOOSTVDDSEL bit of SYSCFG_PMCR. If the switch is closed the switch characteristics are given in the table below. 6.3.17 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 50: I/O static characteristics). Unless otherwise specified, the parameters given in Table 56 are derived from tests performed under the ambient temperature and VDD supply voltage conditions summarized in Table 12: General operating conditions. Table 55. Pxy_C and Pxy analog switch characteristics Parameter Conditions Min Typ Max Unit Switch impedance Switch control boosted - - 315 Ω Switch control not boosted VDDSWITCH > 2.7 V - - 315 VDDSWITCH > 2.4 V - - 335 VDDSWITCH > 2.0 V - - 390 VDDSWITCH > 1.8 V - - 445 VDDSWITCH > 1.62 V - - 550 Table 56. NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit RPU(2) Weak pull-up equivalent resistor(1) 1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order) . VIN = VSS 30 40 50 ㏀ VF(NRST)(2) 2. Guaranteed by design. NRST Input filtered pulse 1.71 V < VDD < 3.6 V - - 50 ns VNF(NRST)(2) NRST Input not filtered pulse 1.71 V < VDD < 3.6 V 350 - - 1.62 V < VDD < 3.6 V 1000 - - |
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