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STM32H723VG Datasheet(PDF) 166 Page - STMicroelectronics |
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STM32H723VG Datasheet(HTML) 166 Page - STMicroelectronics |
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166 / 227 page ![]() Electrical characteristics STM32H723xE/G 166/227 DS13313 Rev 2 CADC Internal sample and hold capacitor -- 5 - pF tADCV REG_ STUP ADC LDO startup time -- 5 10 µs tSTAB ADC power- up time LDO already started 1 - - con- version cycle tOFF_ CAL Offset calibration time - 135 - - 1/fADC tLATR Trigger conversion latency for regular and injected channels without aborting the conversion CKMODE = 00 1.5 2 2.5 CKMODE = 01 - - 2.5 CKMODE = 10 - - 2.5 CKMODE = 11 - - 2.25 tLATR INJ Trigger conversion latency for regular and injected channels when a regular conversion is aborted CKMODE = 00 2.5 3 3.5 CKMODE = 01 - - 3.5 CKMODE = 10 - - 3.5 CKMODE = 11 - - 3.25 tS Sampling time - 2.5 - 640.5 tCONV Total conversion time (including sampling time) N-bits resolution tS + 0.5 + N -- IDDA_ D(ADC) ADC consumption on VDDA and VREF, Differential mode fS= 5 MSPS - 430 - µA fS = 1 MSPS - 133 - fS = 0.1 MSPS - 51 - IDDA_ SE (ADC) ADC consumption on VDDA and VREF, Single- ended mode fS= 5 MSPS - 350 - fS = 1 MSPS - 122 - fS = 0.1 MSPS - 47 - IDD (ADC) ADC consumption on VDD per fADC -- 2.4 - µA/ MHz 1. Guaranteed by design. 2. The voltage booster on ADC switches must be used for VDDA < 2.4 V (embedded I/O switches). 3. Depending on the package, VREF+ can be internally connected to VDDA and VREF- to VSSA. 4. Guaranteed by characterization for BGA and CSP packages. The values for LQFP packages may be different. Table 82. 12-bit ADC characteristics(1)(2) (continued) Sym- bol Parameter Conditions Min Typ Max Unit |
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