STM32H723VG datasheet(186/227 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32H723xE/G

186/227

DS13313 Rev 2

6.3.34

LCD-TFT controller (LTDC) characteristics

Unless otherwise specified, the parameters given in Table 101 for LCD-TFT are derived

from tests performed under the ambient temperature, fHCLK frequency and VDD supply

voltage summarized in Table 12: General operating conditions, with the following

configuration:

•

LCD_CLK polarity: high

•

LCD_DE polarity: low

•

LCD_VSYNC and LCD_HSYNC polarity: high

•

Pixel formats: 24 bits

•

Output speed is set to OSPEEDRy[1:0] = 11

•

Capacitive load CL=30 pF

•

Measurement points are done at CMOS levels: 0.5VDD

•

IO Compensation cell activated.

•

HSLV activated when VDD ≤ 2.7 V

•

VOS level set to VOS0

Table 101. LTDC characteristics(1)

Symbol

Parameter

Min

Max

Unit

fCLK

LTDC clock

output

frequency

2.7<VDD<3.6 V, 20 pF

150

MHz

2.7<VDD<3.6 V

133

1.62<VDD<3.6 V

90/76.5(2)

DCLK

LTDC clock output duty cycle

tw(CLKH),

tw(CLKL)

Clock High time, low time

tw(CLK)//2−0.5

tw(CLK)/2+0.5

tv(DATA)

Data output valid time

2.7<VDD<3.6 V

2.0

1.62<VDD<3.6 V

2.5/6.5(2)

th(DATA)

Data output hold time

tv(HSYNC),

tv(VSYNC),

tv(DE)

HSYNC/VSYNC/DE output

valid time

2.7<VDD<3.6 V

1.5

1.62<VDD<3.6 V

2.0

th(HSYNC),

th(VSYNC),

th(DE)

HSYNC/VSYNC/DE output hold time

1. Guaranteed by characterization results.

2. This value is valid when PA[9], PA[10], PA[11], PA[12], PA[15], PB[11], PH[4], PJ[8], PJ[9], PJ[10], PJ[11], PK[0], PK[1] or

PK[2] is used.

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