FSL518APG datasheet(17/27 Pages) ONSEMI

17 / 27 page

FSL518H, FSL538H, FSL518A, FSL538A

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Figure 39. Burst−mode Behavior

VCOMP

VBURL

VBURH

IDS

PWM

disabled

PWM

disabled

VBURL and VBURH can be adjusted LINE-pin voltage

detected. It is provided for tuning light load efficiency and

acoustic noise. By adjusting VBURL, minimum peak value

of drain current of each switching cycle is adjusted as

described in Equation 1.

IDRAIN.PEAK.BURL +

VBURL

4 @ 0.6 @

ILIM

(eq. 1)

Line Compensation

Propagation delay in turning off power MOSFET makes

drain current exceed current limit by an amount that related

to slope of drain current. The device adjusts its internal

current-limit reference voltage according to duty cycle to

compensate the effect of propagation delay. As a result, the

delivered output power is kept under control across different

input voltage conditions.

Protections

Over Load Protection (OLP)

VCOMP will be pulled higher than VOLP when drain

current hits current limit and switching frequency operates

at its highest range. If the condition continues for tD-OLP,

OLP will be triggered and switching operation is stopped as

shown in Fig. 40.

The figure also shows typical protection mode behavior of

the IC. The operation current is supplied by HV current

source for tAR that can extend the restart period to reduce

average power dissipation when fault is still present. After

tAR, VCC drops to VCC-STOP to reset protective operation

and then, controller will be restarted.

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