FSL518APG datasheet(23/27 Pages) ONSEMI

23 / 27 page

FSL518H, FSL538H, FSL518A, FSL538A

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PCB Layout Recommendations

Hereafter are a few hints that would help designers to

make their SMPS working better.

• High-frequency switching current/voltage makes PCB

layout a very important design issue. Good PCB layout

minimizes EMI (Electromagnetic Interference) and helps

the

power

supply

survive

during

surge/ESD

(ElectroStatic Discharge) tests.

• To improve EMI performance and reduce line frequency

ripples, the output of the bridge rectifier should be

connected to capacitor CDC as close as possible.

• The high-frequency current loop is formed from the

beginning of bridge rectifier, CDC, power transformer,

Integrated MOSFET and return to GND of CDC. The area

enclosed by this current loop should be designed as small

as possible to reduce conduction and radiation noise.

Keep the traces (especially 2a

" 2b " 1) short, direct,

and wide. High-voltage traces related the drain of

MOSFET and RCD snubber should be kept far way from

control circuits to prevent unnecessary interference. If

a heatsink is used for MOSFET, connect this heatsink to

power ground.

• As indicated by 2a, the ground of control circuits should

be connected first, then to other circuitry.

• Place CVcc as close to VCC pin of the FSL5x8H/A as

possible for good decoupling. It is recommended to use

a few of micro-farad capacitor and 100 nF ceramic

capacitor for high frequency noise decoupling as well.

There are some suggestions for grounding connection.

• GND: There are two kinds of GND in power conversion

board and should be separated for avoiding interference

and better performance.

• Regarding the ESD discharge path, the charges go from

secondary, through the transformer stray capacitance, to

GND first, and back to mains. It should be noted that

control circuits should not be placed on the discharge

path. Point discharge for common choke can decrease

high-frequency impedance and increase ESD immunity.

• 3 should be a point-discharger route to bypass the static

electricity energy. It is suggested to map out this discharge

route.

• Should a Y-cap be required between primary and

secondary, connect this Y-cap to the positive terminal of

CDC. If this Y-cap is connected to primary GND, it should

be connected to the negative terminal of CDC (GND)

directly. Point discharge of this Y-cap helps for ESD;

however, the creepage between these two pointed ends

should be at least 5 mm according to safety requirements.

Thermal Considerations

Power MOSFET dissipates heat during switching

operation. If chip temperature exceed TSD, thermal

shutdown would be triggered and FSL5x8 stops operating to

protect itself from damage. The path of lowest thermal

impedance from FSL5x8’s chip to external are DRAIN pins.

It is recommended to increase area of connected copper to

DRAIN pin as much as possible.

Figure 48. Layout Considerations

Enlarge DRAIN pin pattern

for better heat emission

FSL518APG Datasheet(PDF) 23 Page - ON Semiconductor

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