FSL518APG datasheet(21/27 Pages) ONSEMI

21 / 27 page

FSL518H, FSL538H, FSL518A, FSL538A

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DESIGN CONSIDERATIONS

Peripheral Components

While designing flyback converters using FSL5x8H/A,

there are some design considerations on selecting value and

rating of components and PCB (Printed Circuit Board)

layout as the following.

• Input/Output Capacitor

It is typical to select the input capacitor as 2~3

mF per

watt of peak input power for universal input range

(85−265 VRMS) and 1 mF per watt of peak input power for

European high input voltage range (195−265 V RMS).

The minimum DC link voltage is obtained as:

VDC

min

2 @ Vline

min

Pin @ 1 * Dch

fL @ CDC

(eq. 2)

where Dch is the DC link capacitor charging duty ratio

which is typically about 0.2. fL is line voltage frequency.

Considering the output voltage ripple, capacitance at

the output terminal can be determined as the following.

For better voltage ripple at output terminal, low ESR

(Effective Series Resistance) type capacitor is

recommended.

COUT +

0.25 @ IOUT

VOUT*ripple @ fmin

(eq. 3)

where IOUT is a max output load current, VOUT-ripple is

deviation of a ripple voltage and fmin should minimum

freqeuncy between operating frequency deviation.

• VCC Capacitance

FSL5x8 includes HV start-up circuit providing startup

current, which determine startup time. It can be calculated

with ICH and VCC capacitance. The typical value of VCC

capacitor is selected in a range of 10 to 47

mF. It is

recommended that VCC capacitor and FSL5x8 should be

placed as close as possible to reject noise decoupling.

Start−up Time +

CVCC @ VCC*START

ICH

(eq. 4)

• Consideration on Designing BI/BO/LOVP

Line input voltage can be detected for brown-in (BI),

brown-out (BO) and input line over-voltage protection

(LOVP) by connecting LINE pin with dividing resisters

linking to input bulk capacitor. Each level of BI and

LOVP can be determined as following. Meanwhile,

CLINE-F should be choosen considering some noises on

the line induced by switching of the main switch and etc.

It is typical to select 3~5 times of time constant higher

than switching frequency.

VBULK

RLINE-lower

RLINE-upper

CLINE−F

LINE

Figure 45. LINE Pin Settle for BI/BO/LOVP

Brown−in AC Voltage +

(eq. 5)

VLINE−BI

RLINE−upper ) RLINE−lower

RLINE−lower

Line OVP AC Voltage +

(eq. 6)

VLINE−OVP

RLINE−upper ) RLINE−lower

RLINE−lower

(eq. 7)

CLINE−F +

RLINE−upper RLINE−lower @ fSW

• Selecting FB/COMP and Consideration when One of

Both is Selected

For non-isolated converters, connects the output

voltage divider to FB pin. For isolated converters, FB pin

should be connected to GND, and the external feedback

circuit should connect to COMP as well.

• Preventing Audible Noise

Even though the switching frequency of the FSL5x8 is

above the range of human hearing, audible noise can be

generated during transient or burst operation. In most

flyback converters, the major noise sources are

transformers and capacitors. Transformers produce

audible noise, since they contain many physically

movable elements, such as coils, isolation tapes and

bobbins. The most effective way to reduce the audible

noise in the transformer is to remove the possibility of

physical movement of the transformer elements by using

adhesive material or by varnishing.

Ceramic capacitors can also produce audible noise,

because of their piezoelectric characteristics. By

replacing the ceramic capacitor with a film capacitor, the

audible noise can be reduced. Another way to lower

audible noise is to reduce the snubber capacitor value,

FSL518APG Datasheet(PDF) 21 Page - ON Semiconductor

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