PIMXRT516SCVM2A datasheet(83/124 Pages) NXP

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Electrical characteristics

i.MX RT1160 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 04/2021

NXP Semiconductors

Figure 36. LPSPI Master mode timing (CPHA = 1)

Table 82. LPSPI Slave mode timing

Number

Symbol

Description

Min.

Max.

Units

Note

1fSCK

Frequency of operation

fperiph / 2

MHz

1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be

guaranteed this limit is not exceeded.

2tSCK

SCK period

2 x tperiph

—ns

2 tperiph = 1000 / fperiph

3tLead

Enable lead time

—

tperiph

—

4tLag

Enable lag time

—

tperiph

—

5tWSCK

Clock (SCK) high or low time

tSCK / 2 - 5

—

6tSU

Data setup time (inputs)

2.7

—

7tHI

Data hold time (inputs)

3.8

—

8ta

Slave access time

—

tperiph

3 Time to data active from high-impedance state

9tdis

Slave MISO disable time

—

tperiph

4 Hold time to high-impedance state

Data valid (after SCK edge)

—

14.5

—

tHO

Data hold time (outputs)

—

MSB IN

BIT 6 . . . 1

MASTER MSB OUT

MASTER LSB OUT

PORT DATA

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

(OUTPUT)

(CPOL=0)

SCK

(CPOL=1)

PCS

(OUTPUT)

SOUT

(OUTPUT)

SIN

(INPUT)

LSB IN

BIT 6 . . . 1

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