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WM2130CDT Datasheet(PDF) 6 Page - Wolfson Microelectronics plc |
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WM2130CDT Datasheet(HTML) 6 Page - Wolfson Microelectronics plc |
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6 / 20 page ![]() WM2130 Production Data WOLFSON MICROELECTRONICS LTD PD Rev 1.2 April 2001 6 Sample 1 Sample 5 Sample 4 Sample 3 Sample 2 tCLK tCL tCH Digital Output tD Pipeline Delay Sample 1 Sample 2 Note: All timing measurements are based on 50% of edge transition CLK Analogue Input at AIN Figure 1 Output Timing Test Conditions: AVDD = DVDD = 3.0V, fCLK = 30MHz, 50% duty cycle, MODE = AVDD, REFTS = 2.5V, REFBS = 0.5V, TA = TMIN to TMAX, unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Clock Clock period tCLK 33 ns Clock high time tCH 15 16.5 ns Clock low time tCL 15 16.5 ns Timing Pipeline delay 3 CLK cycles Clock to data valid tD 25 ns Output disable to hi-Z output tDZ 020 ns Output enable to data valid tDEN 020 ns |
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