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PCMD3140IRTER Datasheet(PDF) 78 Page - Texas Instruments |
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PCMD3140IRTER Datasheet(HTML) 78 Page - Texas Instruments |
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78 / 106 page  Figure 7-109. DSP_CFG1 Register (continued) DVOL_GANG BIQUAD_CFG[1:0] DISABLE_SOF T_STEP RESERVED RESERVED RESERVED RESERVED R/W-0b R/W-10b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b Table 7-86. DSP_CFG1 Register Field Descriptions Bit Field Type Reset Description 7 DVOL_GANG R/W 0b DVOL control ganged across channels. 0d = Each channel has its own DVOL CTRL settings as programmed in the CHx_DVOL bits 1d = All active channels must use the channel 1 DVOL setting (CH1_DVOL) irrespective of whether channel 1 is turned on or not 6-5 BIQUAD_CFG[1:0] R/W 10b Number of biquads per channel configuration. 0d = No biquads per channel; biquads are all disabled 1d = 1 biquad per channel 2d = 2 biquads per channel 3d = 3 biquads per channel 4 DISABLE_SOFT_STEP R/W 0b Soft-stepping disable during DVOL change, mute, and unmute. 0d = Soft-stepping enabled 1d = Soft-stepping disabled 3 RESERVED R/W 0b Reserved bit; Write only reset value 2 RESERVED R/W 0b Reserved bit; Write only reset value 1 RESERVED R/W 0b Reserved bit; Write only reset value 0 RESERVED R/W 0b Reserved bit; Write only reset value 7.6.1.43 IN_CH_EN Register (Address = 0x73) [Reset = 0xC0] IN_CH_EN is shown in Figure 7-110 and described in Table 7-87. Return to the Table 7-44. This register is the input channel enable configuration register. Figure 7-110. IN_CH_EN Register 7 6 5 4 3 2 1 0 IN_CH1_EN IN_CH2_EN IN_CH3_EN IN_CH4_EN RESERVED R/W-1b R/W-1b R/W-0b R/W-0b R-0000b Table 7-87. IN_CH_EN Register Field Descriptions Bit Field Type Reset Description 7 IN_CH1_EN R/W 1b Input channel 1 enable setting. 0d = Channel 1 is disabled 1d = Channel 1 is enabled 6 IN_CH2_EN R/W 1b Input channel 2 enable setting. 0d = Channel 2 is disabled 1d = Channel 2 is enabled 5 IN_CH3_EN R/W 0b Input channel 3 (PDM only) enable setting. 0d = Channel 3 is disabled 1d = Channel 3 is enabled 4 IN_CH4_EN R/W 0b Input channel 4 (PDM only) enable setting. 0d = Channel 4 is disabled 1d = Channel 4 is enabled 3-0 RESERVED R 0000b Reserved bits; Write only reset value PCMD3140 SBASA64A – DECEMBER 2020 – REVISED JUNE 2021 www.ti.com 78 Submit Document Feedback Copyright © 2021 Texas Instruments Incorporated Product Folder Links: PCMD3140 |
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