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PCMD3140IRTER Datasheet(PDF) 23 Page - Texas Instruments

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Part # PCMD3140IRTER
Description  PCMD3140 Quad-Channel, PDM Input to TDM or I2S Output Converter
PDF  106 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCMD3140IRTER Datasheet(HTML) 23 Page - Texas Instruments

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7.3.2 Phase-Locked Loop (PLL) and Clock Generation
The device has a smart auto-configuration block to generate all necessary internal clocks required for the PDM
clock generation and the digital filter engine used for signal processing. This configuration is done by monitoring
the frequency of the FSYNC and BCLK signal on the audio bus.
The device supports the various output data sample rates (of the FSYNC signal frequency) and the BCLK to
FSYNC ratio to configure all clock dividers, including the PLL configuration, internally without host programming.
Table 7-6 and Table 7-7 list the supported FSYNC and BCLK frequencies.
Table 7-6. Supported FSYNC (Multiples or Submultiples of 48 kHz) and BCLK Frequencies
BCLK TO
FSYNC
RATIO
BCLK (MHz)
FSYNC
(8 kHz)
FSYNC
(16 kHz)
FSYNC
(24 kHz)
FSYNC
(32 kHz)
FSYNC
(48 kHz)
FSYNC
(96 kHz)
FSYNC (192
kHz)
FSYNC (384
kHz)
FSYNC (768
kHz)
16
Reserved
0.256
0.384
0.512
0.768
1.536
3.072
6.144
12.288
24
Reserved
0.384
0.576
0.768
1.152
2.304
4.608
9.216
18.432
32
0.256
0.512
0.768
1.024
1.536
3.072
6.144
12.288
24.576
48
0.384
0.768
1.152
1.536
2.304
4.608
9.216
18.432
Reserved
64
0.512
1.024
1.536
2.048
3.072
6.144
12.288
24.576
Reserved
96
0.768
1.536
2.304
3.072
4.608
9.216
18.432
Reserved
Reserved
128
1.024
2.048
3.072
4.096
6.144
12.288
24.576
Reserved
Reserved
192
1.536
3.072
4.608
6.144
9.216
18.432
Reserved
Reserved
Reserved
256
2.048
4.096
6.144
8.192
12.288
24.576
Reserved
Reserved
Reserved
384
3.072
6.144
9.216
12.288
18.432
Reserved
Reserved
Reserved
Reserved
512
4.096
8.192
12.288
16.384
24.576
Reserved
Reserved
Reserved
Reserved
1024
8.192
16.384
24.576
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2048
16.384
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table 7-7. Supported FSYNC (Multiples or Submultiples of 44.1 kHz) and BCLK Frequencies
BCLK TO
FSYNC
RATIO
BCLK (MHz)
FSYNC
(7.35 kHz)
FSYNC
(14.7 kHz)
FSYNC
(22.05 kHz)
FSYNC
(29.4 kHz)
FSYNC
(44.1 kHz)
FSYNC
(88.2 kHz)
FSYNC
(176.4 kHz)
FSYNC
(352.8 kHz)
FSYNC
(705.6 kHz)
16
Reserved
Reserved
0.3528
0.4704
0.7056
1.4112
2.8224
5.6448
11.2896
24
Reserved
0.3528
0.5292
0.7056
1.0584
2.1168
4.2336
8.4672
16.9344
32
Reserved
0.4704
0.7056
0.9408
1.4112
2.8224
5.6448
11.2896
22.5792
48
0.3528
0.7056
1.0584
1.4112
2.1168
4.2336
8.4672
16.9344
Reserved
64
0.4704
0.9408
1.4112
1.8816
2.8224
5.6448
11.2896
22.5792
Reserved
96
0.7056
1.4112
2.1168
2.8224
4.2336
8.4672
16.9344
Reserved
Reserved
128
0.9408
1.8816
2.8224
3.7632
5.6448
11.2896
22.5792
Reserved
Reserved
192
1.4112
2.8224
4.2336
5.6448
8.4672
16.9344
Reserved
Reserved
Reserved
256
1.8816
3.7632
5.6448
7.5264
11.2896
22.5792
Reserved
Reserved
Reserved
384
2.8224
5.6448
8.4672
11.2896
16.9344
Reserved
Reserved
Reserved
Reserved
512
3.7632
7.5264
11.2896
15.0528
22.5792
Reserved
Reserved
Reserved
Reserved
1024
7.5264
15.0528
22.5792
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
2048
15.0528
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
The status register ASI_STS (P0_R21) captures the device auto detect result for the FSYNC frequency and
the BCLK to FSYNC ratio. If the device finds any unsupported combinations of FSYNC frequency and BCLK to
FSYNC ratios, the device generates an ASI clock-error interrupt and mutes the record channels accordingly.
The device uses an integrated, low-jitter, phase-locked loop (PLL) to generate internal clocks required for the
PDM clock generation and digital filter engine, as well as other control blocks. The device also supports an
www.ti.com
PCMD3140
SBASA64A – DECEMBER 2020 – REVISED JUNE 2021
Copyright © 2021 Texas Instruments Incorporated
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Product Folder Links: PCMD3140



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