ACE25AA128GFMLTH datasheet(22/71 Pages) ACE

22 / 71 page

ACE25AA128G

Serial NOR Flash Memory

128 Megabits 3.0V Quad I/O Serial Flash Memory with 4KB Uniform Sector

VER 1.1

data byte, the CMP and QE bit will be cleared to 0. As soon as CS# is driven high, the self-timed Write

Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in

progress, the Status Register can still be read to check the value of the Write In Progress (WIP) bit. The

Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is

completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.

The Write Status Register (WRSR) command allows the user to change the values of the Block Protect

(BP4, BP3,BP2, BP1, and BP0) bits, to define the size of the area that is to be treated as read-only, as

defined in Table1. The Write Status Register (WRSR) command also allows the user to set or reset the

Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register

Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected

Mode. The Write Status Register (WRSR) command is not executed once the Hardware Protected Mode

is entered.

Figure5. Write Status Register Sequence Diagram

Figure5a. Write Status Register Sequence Diagram (QPI)

ACE25AA128GFMLTH Datasheet(PDF) 22 Page - ACE Technology Co., LTD.