ACE25AA128GFMLTH datasheet(37/71 Pages) ACE

Part #	ACE25AA128GFMLTH

Description	Serial NOR Flash Memory 128 Megabits 3.0V Quad I/O Serial Flash Memory with 4KB Uniform Sector

PDF	71 Pages

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Manufacturer	ACE [ACE Technology Co., LTD.]

Direct Link	http://www.ace-ele.com

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ACE25AA128G

Serial NOR Flash Memory

128 Megabits 3.0V Quad I/O Serial Flash Memory with 4KB Uniform Sector

VER 1.1

The Chip Erase command sequence: CS# goes low→sending Chip Erase command→CS# goes high.

The command sequence is shown in Figure22. CS# must be driven high after the eighth bit of the

command code has been latch in, otherwise the Chip Erase command is not executed. As soon as CS# is

driven high, the self-timed Chip Erase cycle (whose duration is tCE) is initiated. While the Chip Erase cycle

is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The

Write In Progress (WIP) bit is 1 during the self-timed Chip Erase cycle, and is 0 when it is completed. At

some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip

Erase (CE) command is executed if the Block protected by (BP2, BP1, BP0) bits. The Chip Erase(CE)

command is ignored if one or more sectors are protected. Note: Power disruption during erase operation

will cause incomplete erase, thus recommend to perform a re-erase once power resume.

Figure22. Chip Erase Sequence Diagram

Figure22a. Chip Erase Sequence Diagram (QPI)

ACE25AA128GFMLTH Datasheet(PDF) 37 Page - ACE Technology Co., LTD.