EDSTRG40DILAX datasheet(41/78 Pages) TI

41 / 78 page

GLOSSARY/SYMBOLS, TERMS, AND DEFINITIONS

1–33

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LSB:

Least significant bit

LSbyte:

Least significant byte

machine code:

The actual bytes read by the CPU during an instruction execution; usually read by a programmer

as hexadecimal bytes

mask-programmed read-only memory (Mask-ROM):

A read-only memory in which the data content of each cell

is determined during manufacture by the use of a mask, the data content thereafter being unalterable

MC pin:

Mode control pin. The pin that determines the operating mode of the TMS370 device, depending on the

voltage applied to the pin. Twelve volts on the MC pin after reset places the processor in the write-protection over-

ride (WPO) mode.

memory:

A medium capable of storing information that can be retrieved.

memory map:

A description of the addresses of the various sections and features of the TMS370 processor. The

map depends on the operating mode.

microcomputer mode with external expansion:

An operating mode in which the address, control, and data

memory extend off-chip to access external memory or peripherals

microcomputer single-chip mode:

An operating mode in which the device uses only on-chip memory

microcontroller programmer:

An interactive, menu-driven system that provides a method of programming

TMS370 family devices and EPROMs directly or through an XDS

microprocessor mode with internal-program memory:

An operating mode in which the on-chip program

memory is available to the processor

microprocessor mode without internal-program memory:

An operating mode in which the on-chip program

memory is not available to the processor. The processor must have external memory.

mini-SCI:

The mini-UART function available in the PACT module.

mnemonic:

A symbol that represents the opcode part of an assembly language instruction.

MSB:

Most significant bit

MSbyte:

Most significant byte

multiprocessor communications:

An SCI format option that enables one processor to efficiently send blocks of

data to other processors on the same serial link

nested interrupts:

The ability of an interrupt to suspend the service routine of a prior interrupt. Nested interrupts

are implemented in TMS370 devices by executing an interrupt-service routine that uses the EINT, EINTL, or

EINTH instructions to set the global-interrupt-enable bits in the status register.

nonmaskable interrupt (NMI):

An interrupt that causes the processor to execute the NMI routine. On TMS370

devices, INT1 can be configured as an NMI.

nonreturn to zero (NRZ) format:

A communication format in which the inactive state is a logic state

nonvolatile memory:

A memory in which the data content is maintained whether the power supply is connected

or not

EDSTRG40DILAX Datasheet(PDF) 41 Page - Texas Instruments

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