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ACE25QC200GLFMLTH Datasheet(PDF) 45 Page - ACE Technology Co., LTD.

Part # ACE25QC200GLFMLTH
Description  2M BIT SPI NOR FLASH
PDF  64 Pages
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Manufacturer  ACE [ACE Technology Co., LTD.]
Direct Link  http://www.ace-ele.com
Logo ACE - ACE Technology Co., LTD.

ACE25QC200GLFMLTH Datasheet(HTML) 45 Page - ACE Technology Co., LTD.

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ACE25QC200GL
2M BIT SPI NOR FLASH
VER 1.1
45
Erase Security Registers (44h)
The ACE25QC200GL offers three 512-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other
important information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction
must be executed before the device will accept the Erase Security Register Instruction (Status Register bit
WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“44h” followed by a 24-bit address (A23-A0) to erase one of the three security registers.
Address
A23-16
A15-12
A11-8
A8-0
Security Registers 1
00H
0001
0000
Don’t Care
Security Registers 2
00H
0010
0000
Don’t Care
Security Registers 3
00H
0011
0000
Don’t Care
The Erase Security Register instruction sequence is shown in Figure35. The /CS pin must be driven high
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After /CS is driven high, the self-timed Erase Security Register operation will commence for a time duration
of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read Status
Register instruction may still be accessed for checking the status of the WIP bit. The WIP bit is a 1 during
the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit in
the Status Register is cleared to 0. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be
used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register
(LB3-1 corresponds to S13-11) will be permanently locked, Erase Security Register instruction to that
register will be ignored (Refer to section LB3/LB2/LB1 for detail descriptions).
Figure34. Program/Erase Resume Instruction
Figure35. Erase Security Registers Instruction



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