ACE25QC200GLFMLTH datasheet(12/64 Pages) ACE

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ACE25QC200GL

2M BIT SPI NOR FLASH

VER 1.1

(E)

QE bit

The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad SPI

operation. When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE

bit is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during

standard SPI or Dual SPI operation if the /WP or /HOLD pins directly to the power supply or ground).

(F)

LB3/LB2/LB1 bit

The LB bit is a non-volatile One Time Program (OTP) bit in Status Register (S13-S11) that provide the

write protect control and status to the Security Registers. The default state of LB is 0, the security

registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One

Time Programmable, once it’s set to 1, the Security Registers will become read-only permanently

(LB3-1 corresponds to S13-11).

(G)

SUS1, SUS2 bit

The SUS1 and SUS2 bit are read only bits in the status register2 (S15 and S10) that are set to 1 after

executing a Program/Erase Suspend (75H) instruction (The Erase Suspend will set SUS1 to 1. The

Program Suspend will set the SUS2 to 1). The SUS bits are cleared to 0 by Program/Erase Resume

(7AH) instruction. Software reset (66H/99H) instruction as well as a power-down, power-up cycle.

(H)

Complement Protect (CMP)

The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register. It is used in

conjunction with BP4, BP3, BP2, BP1 and BP0 bits to provide more flexibility for the array protection.

Please refer to the Status Register Memory Protection table for details. The default setting is CMP=0.

ACE25QC200GLFMLTH Datasheet(PDF) 12 Page - ACE Technology Co., LTD.