SH7750 datasheet(39/1039 Pages) RENESAS

39 / 1039 page

Rev. 6.0, 07/02, page xxxvii of I

Figure 13.26

Example of 64-Bit Data Width Synchronous DRAM Connection (Area 3) .... 414

Figure 13.27

Example of 32-Bit Data Width Synchronous DRAM Connection (Area 3) .... 415

Figure 13.28

Basic Timing for Synchronous DRAM Burst Read ......................................... 417

Figure 13.29

Basic Timing for Synchronous DRAM Single Read........................................ 418

Figure 13.30

Basic Timing for Synchronous DRAM Burst Write ........................................ 419

Figure 13.31

Basic Timing for Synchronous DRAM Single Write....................................... 421

Figure 13.32

Burst Read Timing ........................................................................................... 423

Figure 13.33

Burst Read Timing (RAS Down, Same Row Address) .................................... 424

Figure 13.34

Burst Read Timing (RAS Down, Different Row Addresses)........................... 425

Figure 13.35

Burst Write Timing .......................................................................................... 426

Figure 13.36

Burst Write Timing (Same Row Address) ....................................................... 427

Figure 13.37

Burst Write Timing (Different Row Addresses) .............................................. 428

Figure 13.38

Burst Read Cycle for Different Bank and Row Address Following

Preceding Burst Read Cycle............................................................................. 430

Figure 13.39

Auto-Refresh Operation ................................................................................... 432

Figure 13.40

Synchronous DRAM Auto-Refresh Timing..................................................... 432

Figure 13.41

Synchronous DRAM Self-Refresh Timing ...................................................... 434

Figure 13.42 (1) Synchronous DRAM Mode Write Timing (PALL) ......................................... 436

Figure 13.42 (2) Synchronous DRAM Mode Write Timing (Mode Register Set) ...................... 437

Figure 13.43

Basic Timing of Synchronous DRAM Burst Read (Burst Length = 4)............ 438

Figure 13.44

Basic Timing of a Burst Write to Synchronous DRAM................................... 440

Figure 13.45

Example of the Connection of Synchronous DRAM with 64-bit Bus Width

(256 Mbits)....................................................................................................... 441

Figure 13.46

Burst ROM Basic Access Timing .................................................................... 442

Figure 13.47

Burst ROM Wait Access Timing ..................................................................... 443

Figure 13.48

Burst ROM Wait Access Timing ..................................................................... 444

Figure 13.49

Example of PCMCIA Interface ........................................................................ 448

Figure 13.50

Basic Timing for PCMCIA Memory Card Interface........................................ 449

Figure 13.51

Wait Timing for PCMCIA Memory Card Interface ......................................... 450

Figure 13.52

PCMCIA Space Allocation .............................................................................. 451

Figure 13.53

Basic Timing for PCMCIA I/O Card Interface ................................................ 452

Figure 13.54

Wait Timing for PCMCIA I/O Card Interface ................................................. 453

Figure 13.55

Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ........................ 454

Figure 13.56

Example of 64-Bit Data Width MPX Connection............................................ 456

Figure 13.57

MPX Interface Timing 1

(Single Read Cycle, AnW = 0, No External Wait, Bus Width: 64 Bits) .......... 457

Figure 13.58

MPX Interface Timing 2

(Single Read, AnW = 0, One External Wait Inserted, Bus Width: 64 Bits) ..... 458

Figure 13.59

MPX Interface Timing 3

(Single Write Cycle, AnW = 0, No Wait, Bus Width: 64 Bits)........................ 459

Figure 13.60

MPX Interface Timing 4

(Single Write, AnW = 1, One External Wait Inserted, Bus Width: 64 Bits) .... 460

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