SH7750 datasheet(21/1039 Pages) RENESAS

21 / 1039 page

Rev. 6.0, 07/02, page xix of I

Section

Page

Item

Description

22.3.4 Peripheral Module

Signal Timing

924, 925

Table 22.36 Peripheral

Module Signal Timing (1)

Table newly added

900 to

921, 923

Figures 22.37 to 22.58,

Figure 22.60

Titles amended

930

Figure 22.62 RTC Oscillation

Settling Time at Power-On

Amended

932

Figure 22.66(b)

'%5(4/75

Input Timing and

%$9/

Output Timing

Newly added

Appendix A Address List

937 to

942

Table A.1 Address List

BCR4, RCR3, RYRAR,

SDINT and Notes

added

BCR3 area 7 address

amended

DMAC, INTC, CPG,

TMU table added

Appendix B Package

Dimensions

943, 944

Figure B.1 Package

Dimensions (256-Pin BGA)

Figure B.2 Package

Dimensions (208-Pin QFP)

Amended

Appendix C Mode Pin

Settings

946

Clock Modes

Table 10.3 (1), (2)

inserted

947

Area 0 Bus Width

Area 0 memory type

deleted and data

integrated into area 0

bus width table

Appendix D

&.,25(1% Pin

Configuration

948

Figure D.1

&.,25(1% Pin

Configuration

Amended

Appendix E Pin Functions

950 to

952

Table E.1 Pin States in

Reset, Power-Down State,

and Bus-Released State

Sleep row deleted

D40–D51 deleted

Notes added

Appendix F Synchronous

DRAM Address

Multiplexing Tables

970, 971

(17) BUS 64

(128M: 4M × 8b × 4) × 8

(SH7750R only)

(18) BUS 64

(256M: 4M × 16b × 4) × 4

(SH7750R only)

Newly added

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