AS4LC256K16EO datasheet(8/25 Pages) ALSC

8 / 25 page

AS4LC256K16EO

4/11/01; V.1.1

Alliance Semiconductor

P. 8 of 25

Notes

1ICC1, ICC3, ICC4, and ICC6 depend on cycle rate.

2ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open.

An initial pause of 200

µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal

refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after

extended periods of bias without clocks (greater than 8 ms).

AC Characteristics assume tT = 5 ns. All AC parameters are measured with a load equivalent to two TTL loads and 60 pF, VIL (min) ≥ GND and VIH (max)

≤ V

CC.

5VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.

Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the

specified tRCD (max) limit, then access time is controlled exclusively by tCAC.

Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the

specified tRAD (max) limit, then access time is controlled exclusively by tAA.

Assumes three state test load (5 pF and a 380

Ω Thevenin equivalent).

9Either tRCH or tRRH must be satisfied for a read cycle.

10 tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels.

11 tWCS, tWCH, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only. If tWS ≥ tWS

(min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the cycle. If tRWD

≥ t

RWD (min), tCWD ≥ tCWD (min) and tAWD ≥ tAWD (min), the cycle is a read-write cycle and the data out will contain data read from the selected cell.

If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.

12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.

13 Access time is determined by the longest of tCAA or tCAC or tCAP.

14 tASC ≥ tCP to achieve tPC (min) and tCAP (max) values.

15 These parameters are sampled and not 100% tested.

Key to switching waveform

Read cycle waveform

Undefined/don’t care

Falling input

Rising input

tRAS

tRC

tRP

tRSH

tRAD

tRCH

tOFF

RAS

UCAS,

Address

I/O

Col Address

Row Address

tCRP

tCSH

tRCD

tASC

tCAH

tCAS

tAR

tRAL

tRAH

tRCS

tAA

tCLZ

tRRH

Data Out

tASR

tRAC

tROH

tOEA

tCAC

tOEZ

LCAS

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