LPC47N237-MD datasheet(84/138 Pages) SMSC

84 / 138 page

3.3v I/O Controller for Port Replicators and Docking Stations

Revision 0.3 (10-26-04)

Page 84

SMSC DS – LPC47N237

DATASHEET

4 Direction Registers

4 Output Type Registers

4 Data Registers

4 Mask Registers

1 Change Status Register

15.3.1 GPIO Pins

Table 15.4 shows the SMBus GPIOs pins.

These pins are powered by VTR

These pins sink 8mA and source 4 mA current under VTR power.

The default on these pins will be input on VTR POR in the LPC47N237.

Table 15.4 – SMBus GPIO Pins

PIN NAME

BUFFER

PWR WELL

DESCRIPTION

GP10 – GP17,

GP20 – GP27,

GP30 – GP37,

GP50 – GP57

IO8

VTR

General Purpose I/O

15.4

SMBus GPIO Registers

See the following sub section for functionality of the SMBus GPIO registers. These registers are in the

SMBus runtime register space and are listed in the “SMBus GPIO Register Map” section.

15.4.1 Direction Registers

There are four direction registers containing bits for each GPIO pin. The Direction register is used to

select input or output direction on the GPIO pin.

15.4.2 Output Type Registers

There are four output type registers containing bits for each GPIO pin. The output type register is used to

selection whether the GPIO pin will be push-pull or open-drain.

15.4.3 Data Registers

The data register will reflect the state of the GPIO input if the GP pin is used as input. It is used to set the

state of the GPIO pin when the GPIO is used as output.

15.4.4 GPIO Mask Registers

There are four mask registers containing bits for each GPIO pin. The bits in the Mask registers are used

to enable/disable wakeup events on the Change Status register. See the “GPIO Change Status Register”

section for more information.

LPC47N237-MD Datasheet(PDF) 84 Page - SMSC Corporation

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