MPC7445 datasheet(36/56 Pages) NXP

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MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5

Freescale Semiconductor

System Design Information

9.1.2

System Bus Clock (SYSCLK) and Spread Spectrum Sources

Spread spectrum clock sources are an increasingly popular way to control electromagnetic interference

emissions (EMI) by spreading the emitted noise to a wider spectrum and reducing the peak noise

magnitude in order to meet industry and government requirements. These clock sources intentionally add

long-term jitter in order to diffuse the EMI spectral content. The jitter specification given in Table 8

considers short-term (cycle-to-cycle) jitter only and the clock generator’s cycle-to-cycle output jitter

should meet the MPC7457 input cycle-to-cycle jitter requirement. Frequency modulation and spread are

separate concerns, and the MPC7457 is compatible with spread spectrum sources if the recommendations

listed in Table 14 are observed.

01101

24x

792

(1600)

1200

(2400)

11101

28x

924

(1866)

1400

(2800)

00110

PLL bypass

PLL off, SYSCLK clocks core circuitry directly

11110

PLL off

PLL off, no core clocking occurs

Notes:

1. Ratios below 5:1 require an AACK delay See

MPC7450 RISC Microprocessor Family Reference Manual, Section

9.3.3, “MPX Bus Address Tenure Termination.”

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,

or VCO frequencies that are not useful, not supported, or not tested for by the MPC7455; see Section 5.2.1, “Clock

AC Specifications,” for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.

However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must be

driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold time

tIXKH (see Table 9). The result will be that the processor bus frequency will be one-half SYSCLK while the internal

processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the MPC7447A regardless of the SYSCLK input.

Table 13. MPC7447A Microprocessor PLL Configuration Example for 1420-MHz Parts (continued)

PLL_

CFG[0:4]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Multiplier

Core-to-

VCO

Multiplier

Bus (SYSCLK) Frequency

MHz

100

MHz

133

MHz

167

MHz

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