ADSP-SC591 datasheet(7/143 Pages) AD

7 / 143 page

Rev. PrD

Page 7 of 143

May 2021

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

Preliminary Technical Data

Generic Interrupt Controller (GIC), PL390

(ADSP-SC59x Only)

The generic interrupt controller (GIC) is a centralized resource

for supporting and managing interrupts. The GIC splits into the

distributor block (GICPORT0) and the central processing unit

(CPU) interface block (GICPORT1).

Generic Interrupt Controller Port0 (GICPORT0)

The GICPORT0 distributor block performs interrupt prioritiza-

tion and distribution to the GICPORT1 CPU interface blocks

that connect to the processors in the system. It centralizes all

interrupt sources, determines the priority of each interrupt, and

forwards the interrupt with the highest priority to the interface,

for priority masking and preemption handling.

Generic Interrupt Controller Port1 (GICPORT1)

The GICPORT1 CPU interface block performs priority masking

and preemption handling for a connected processor in the sys-

tem. GICPORT1 supports 8 software generated interrupts

(SGIs) and 326 shared peripheral interrupts (SPIs).

L2 Cache Controller, PL310 (ADSP-SC59x Only)

The Level 2 (L2) cache controller, PL310 (see Figure 2), works

efficiently with the Arm Cortex-A5 processors that implement

system fabric. The cache controller directly interfaces on the

data and instruction interface. The internal pipelining of the

cache controller is optimized to enable the processors to operate

at the same clock frequency. The cache controller supports the

following:

• Two read/write 64-bit completer ports, one connected to

the Arm Cortex-A5 instruction and data interfaces, and

one connecting the Arm Cortex-A5 and SHARC+ cores for

data coherency

• Two read/write 64-bit requester ports for interfacing with

the system fabric

SHARC PROCESSOR

The SHARC processor integrates a SHARC+ SIMD core, L1

memory crossbar, I-cache/D-cache controller, L1 memory

blocks, and the requester/completer ports, as shown in Figure 3.

The SHARC+ SIMD core block diagram is shown in Figure 4.

The SHARC processor supports a modified Harvard architec-

ture in combination with a hierarchical memory structure. L1

memories typically operate at the full processor speed with little

or no latency.

Figure 3. SHARC Processor Block Diagram

RAM

I-CACHE

RAM

P-CACHE

RAM

P-CACHE

RAM

D-CACHE

RAM

P-CACHE

RAM

P-CACHE

RAM

D-CACHE

RAM

P-CACHE

RAM

P-CACHE

RAM

I/O (32)

INTERNAL MEMORY INTERFACE (IMIF)

I-CACHE/D-CACHE CONTROL

SHARC+

SIMD CORE

COMPLETER

PORT 1

CORE

MMR

DM (64)

PM (64)

PS (64/48)

(32)

REQUESTER

PORT INSTRUCTION

REQUESTER

PORT DATA

I/O (32)

CMD (64)

CMI (64)

SYSTEM FABRIC

SYSCLK

DOMAIN

INTERRUPT

SYSTEM

EVENT

CONTROLLER

SIMD Processor

CCLK DOMAIN

COMPLETER

PORT 2

(MDMA AND

ACCELERATORS)

I/O (32)

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