ADSP-SC591 datasheet(19/143 Pages) AD

19 / 143 page

Rev. PrD

Page 19 of 143

May 2021

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

Preliminary Technical Data

Some advanced features of the EMAC include the following:

• Automatic checksum computation of IP header and IP

payload fields of receive frames

• Independent 32-bit descriptor driven receive and transmit

DMA channels

• Frame status delivery to memory through DMA, including

frame completion semaphores for efficient buffer queue

management in software

• Transmit DMA support for separate descriptors for MAC

header and payload fields to eliminate buffer copy

operations

• Convenient frame alignment modes

• 47 MAC management statistics counters with selectable

clear on read behavior and programmable interrupts on

half maximum value

• Advanced power management

• Magic packet detection and wakeup frame filtering

• Support for 802.3Q tagged VLAN frames

• Programmable MDC clock rate and preamble suppression

Audio Video Bridging (AVB) Support

The 10/100/1000 EMAC supports the following audio video

bridging (AVB) features:

• Separate channels or queues for AV data transfer in

100 Mbps and 1000 Mbps modes

• IEEE 802.1-Qav specified credit-based shaper (CBS) algo-

rithm for the additional transmit channels

• Configuring up to two additional channels (Channel 1 and

Channel 2) on the transmit and receive paths for AV traffic.

Channel 0 is available by default and carries the legacy best

effort Ethernet traffic on the transmit side.

• Separate DMA, transmit and receive FIFO for AVB latency

class

• Programmable control to route received VLAN tagged non

AV packets to channels or queues

Precision Time Protocol (PTP) IEEE 1588 Support

The IEEE 1588 standard is a precision clock synchronization

protocol for networked measurement and control systems. The

processors include hardware support for IEEE 1588 with an

integrated precision time protocol synchronization engine

(PTP_TSYNC).

This engine provides hardware assisted time stamping to

improve the accuracy of clock synchronization between PTP

nodes. The main features of the engine include the following:

• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-

tocol standards

• Hardware assisted time stamping capable of up to 12.5 ns

resolution

• Lock adjustment

• Automatic detection of IPv4 and IPv6 packets, as well as

PTP messages

• Multiple input clock sources (SCLK0, RGMII, RMII, MII

clock, and external clock)

• Programmable pulse per second (PPS) output

• Auxiliary snapshot to time stamp external events

Controller Area Network with Flexible Data-Rate

(CAN FD)

There are two controller area network (CAN) modules. A CAN

controller implements the CAN with flexible data-rate (CAN

FD) and the CAN 2.0B protocol supporting both standard and

extended message frames and long payloads up to 64 bytes,

transferred at rates of up to 8 Mbps. This protocol is an

asynchronous communications protocol used in both industrial

and automotive control systems. The CAN protocol is well

suited for control applications due to the capability to commu-

nicate reliably over a network. This is because the protocol

incorporates CRC checking, message error tracking, and fault

node confinement.

The CAN FD controller offers the following features:

• Flexible mailboxes configurable to store 0 to 8, 16, 32, or 64

bytes

• Dedicated receiver masks for each mailbox

• Flexible message buffers up to 64 buffers of 8 bytes length

each, configurable as receive or transmit

• Programmable transmission priority scheme

• Transceiver delay compensation when transmitting CAN

FD messages at faster data rates

• Memory read accesses error detection and correction

An additional crystal is not required to supply the CAN clock

because it is derived from a system clock through a programma-

ble divider.

Timers

The processors include several timers that are described in the

following sections.

General-Purpose (GP) Timers (TIMER)

There is one general-purpose (GP) timer unit, providing 16 GP

programmable timers. Each timer has an external pin that can

be configured as PWM or timer output, as an input to clock the

timer, or as a mechanism for measuring pulse widths and peri-

ods of external events. These timers can be synchronized to an

external clock input on the TM_TMR[n] pins, an external

TM_CLK input pin, or to the internal SCLK0.

These timer units can be used in conjunction with the UARTs

and the CAN controller to measure the width of the pulses in

the data stream to provide a software autobaud detect function

for the respective serial channels.

The GP timers can generate interrupts to the processor core,

providing periodic events for synchronization to either the sys-

tem clock or to external signals. Timer events can also trigger

other peripherals via the TRU (for instance, to signal a fault).

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