ADSP-SC591 datasheet(1/143 Pages) AD

Part #	ADSP-SC591

Description	SHARC Dual-Core DSP with Arm Cortex-A5

PDF	143 Pages

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Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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SHARC, SHARC+, and the SHARC logo are registered trademarks of Analog Devices, Inc.

Preliminary Technical Data

SHARC+ Dual-Core

DSP with Arm Cortex-A5

ADSP-21591/21593/21594/ADSP-SC591/SC592/SC594

Rev. PrD

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SYSTEM FEATURES

Dual-enhanced SHARC+ floating-point cores

High performance SHARC+ cores (up to 1 GHz each)

Up to 5 Mb (640 kB) L1 SRAM memory per core with parity

(optional ability to configure as cache)

32-bit, 40-bit, and 64-bit floating-point support

32-bit fixed-point support

Byte, short word, word, and long word addressability

Arm Cortex-A5 core

Up to 1 GHz/1600 DMIPS with NEON/VFPv4-D16

32 kB L1 instruction and data caches with parity

256 kB L2 cache with parity

Powerful DMA system with 8 MemDMAs

On-chip memory protection

Integrated safety features

17 mm × 17 mm, 400-ball BGA_ED (0.8 mm pitch),

RoHS compliant

MEMORY

Large on-chip Level 2 (L2) SRAM with ECC protection, up to

2MB

One Level 3 (L3) interface providing 16-bit interface to

DDR3/ DDR3L SDRAM devices

ADDITIONAL FEATURES

ADSP-2156x pin-compatible package options

Enhanced FIR and IIR accelerators running up to 1 GHz

Security and protection

Cryptographic hardware accelerators

Fast secure boot with IP protection

Support for Arm TrustZone

APPLICATIONS

Automotive: audio amplifier, head unit, ANC/RNC, rear seat

entertainment, digital cockpit, ADAS

Consumer: AVRs, mixing consoles, microphone arrays,

conferencing systems

Figure 1. ADSP-SC594 (Full-Featured Model) Processor Block Diagram

PERIPHERALS

SYSTEM

L2 MEMORY

L3 MEMORY

INTERFACE

DDR3/DDR3L

DATA

16

SYSTEM CROSSBAR AND DMA SUBSYSTEM

SRAM

(ECC)

SYSTEM CONTROL

SYSTEM PROTECTION UNIT (SPU)

SECURITY AND PROTECTION

Arm® TrustZone® SECURITY

DUAL CRC (WITH MemDMA)

WATCHDOGS

THERMAL MONITOR UNIT (TMU)

OTP MEMORY

SYSTEM MEMORY

PROTECTION UNIT (SMPU)

L1 SRAM (PARITY)

5 Mb (640 kB)

SRAM/CACHE

CORE 1

S

(UP TO 1 GHz)

BOOT ROM

UP TO

40

CLOCK GENERATION UNIT (CGU)

CLOCK, RESET, AND POWER

RESET CONTROL UNIT (RCU)

Arm® CoreSight

TM

DEBUG UNIT

CLOCK DISTRIBUTION

UNIT (CDU)

DYNAMIC POWER MANAGEMENT

(DPM)

SYSTEM WATCHPOINT UNIT

(SWU)

TRIGGER ROUTING (TRU)

SYS EVENT CORE 0 (GIC)

PROGRAM FLOW

SYS EVENT CORES 1-2 (SEC)

32 kB L1 I-CACHE

32 kB L1 D-CACHE

L1 CACHE (PARITY)

L2 CACHE

256 kB (PARITY)

CORE 0

(UP TO 1 GHz)

Arm

Cortex-A5

L1 SRAM (PARITY)

5 Mb (640 kB)

SRAM/CACHE

CORE 2

ENCRYPTION/DECRYPTION

FAULT MANAGEMENT UNIT (FMU)

FIR

(UP TO

1 GHz)

4× IIR

(UP TO

1 GHz)

ACCELERATORS

FIR

(UP TO

1 GHz)

4× IIR

(UP TO

1 GHz)

ACCELERATORS

®

S

(UP TO 1 GHz)

G

P

I

O

UP TO

135

2× LINK PORTS

4× UARTs

16× TIMERS + 1× COUNTER

1× EPPI

2× CAN FD

MLB 6-PIN

2× EMAC

32x CORE FLAGS I/O

2× SPI + 2× QUAD SPI +

1× OCTAL SPI

6× I

2C

1× USB 2.0 HS OTG

CONTROLLER

MLB 3-PIN

HADC (8-CHANNEL, 12-BIT)

UP TO

8

6

UP TO 2 MB

ASRC

8× PAIRS

2× S/PDIF Rx/Tx

8× PRECISION CLOCK

GENERATORS

FULL SPORT

0-7

2× 4-CHANNEL

PDM MIC INPUT

SRU

DAI0

DAI1

DRU

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