ICS843404 datasheet(10/19 Pages) ICST

10 / 19 page

843404AG

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 17, 2005

Integrated

Circuit

Systems, Inc.

ICS843404

LVCMOS/CRYSTAL-TO-3.3V LVPECL AND

LVDS CLOCK GENERATOR

APPLICATION INFORMATION

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS843404 provides sepa-

rate power supplies to isolate any high switching

noise from the outputs to the internal PLL. V

DD, VDDA, and

DDO_X should be individually connected to the power sup-

ply plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 1 illustrates how

a 24

Ω resistor along with a 10µF and a .01μF bypass

capacitor should be connected to each V

DDA. The 24Ω resis-

tor can also be replaced by a ferrite bead.

POWER SUPPLY FILTERING TECHNIQUES

FIGURE 1. POWER SUPPLY FILTERING

DDA

μF

.01

μF

3.3V

.01

μF

CRYSTAL INPUT INTERFACE

The ICS843404 has been characterized with 18pF parallel

resonant crystals. The capacitor values shown in Figure 2

Figure 2. CRYSTAL INPUt INTERFACE

below were determined using a 25.5MHz 18pF parallel

resonant crystal and were chosen to minimize the ppm

error.

ICS843404

18p

18pF Parallel Crystal

22p

XTAL_OUT

XTAL_IN

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